Finding best voltage and frequency to shorten power-constrained test time

P. Venkataramani, S. Sindia, V. Agrawal
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引用次数: 11

Abstract

In a digital test, supply voltage (VDD), clock frequency (ftest), peak power (PMAX) and test time (TT) are related parameters. For a given limit PMAX = PMAX func, normally set by functional specification, we find the optimum VDD = VDDopt and ftest = fopt to minimize TT. A solution is derived analytically from the technology-dependent characterization of semiconductor devices. It is shown that at VDDopt the peak power any test cycle consumes just equals PMAX func and ftest is fastest that the critical path at VDDopt will allow. The paper demonstrates how test parameters can be obtained numerically from MATLAB, or experimentally by bench test equipment like National Instruments' ELVIS. This optimization can cut the test time of ISCAS'89 benchmarks in 180nm CMOS into half.
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寻找最佳电压和频率以缩短功率受限的测试时间
在数字测试中,电源电压(VDD)、时钟频率(ftest)、峰值功率(PMAX)和测试时间(TT)是相关参数。对于给定的极限PMAX = PMAX函数,通常由功能规范设置,我们找到最优的VDD = VDDopt和ftest = fopt来最小化TT。从半导体器件的技术依赖特性中导出了一个解析的解决方案。结果表明,在VDDopt时,任何测试周期消耗的峰值功率正好等于PMAX函数,并且ftest是VDDopt时关键路径允许的最快速度。本文阐述了如何利用MATLAB软件进行数值计算,或利用美国国家仪器公司的ELVIS等台架测试设备进行实验。此优化可将ISCAS'89在180nm CMOS上的基准测试时间缩短一半。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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