Characterization and compensation of performance variability using on-chip monitors

Abstract

Aggressive technology scaling and strong demand for lowering supply voltage impose a serious challenge in achieving robust and energy-efficient circuit operation. This paper first overviews circuit techniques for variability resilience including on-chip circuits for performance and variability monitoring. We then focus on on-chip delay cells for transistor performance estimation and homogeneous and inhomogeneous ring oscillators for Die-to-Die (D2D) and Within-Die (WID) variability extraction. We also explain topology-reconfigurable on-chip monitors for in-situ variability characterization which can be used for D2D and WID variability modeling. The monitor can also be used for monitoring temporal variability such as Random Telegraph Noise (RTN). Compensation of performance variability can be done by a localized body biasing with on-chip monitors. A proof-of-concept circuit fabricated in a 65 nm process will be demonstrated such that a test chip fabricated at the slow process corner can achieve a target performance under the typical process condition by the compensation.