Càndid Reig, F. Pardo, J. Boluda, F. Vegara, M. Cubells-Beltrán, Javio Sanchis, S. Abrunhosa, S. Cardoso
{"title":"Advanced Giant Magnetoresistance (GMR) sensors for Selective-Change Driven (SCD) circuits","authors":"Càndid Reig, F. Pardo, J. Boluda, F. Vegara, M. Cubells-Beltrán, Javio Sanchis, S. Abrunhosa, S. Cardoso","doi":"10.1109/CDE52135.2021.9455731","DOIUrl":null,"url":null,"abstract":"Nowadays, bio-inspiration is driving novel sensors designs, beyond vision sensors. By taking advantage of their compatibility with standard CMOS technologies, the integration of giant magneto-resistance (GMR) based magnetic sensors within such event-driven approaches is proposed. With this aim, several topologies of such GMR sensors have been designed, fabricated and characterized. In addition, integrated circuit interfaces of a standard CMOS technology are also proposed. Their suitability for this approach is then demonstrated by means of Cadence IC simulations.","PeriodicalId":267404,"journal":{"name":"2021 13th Spanish Conference on Electron Devices (CDE)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 13th Spanish Conference on Electron Devices (CDE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CDE52135.2021.9455731","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Nowadays, bio-inspiration is driving novel sensors designs, beyond vision sensors. By taking advantage of their compatibility with standard CMOS technologies, the integration of giant magneto-resistance (GMR) based magnetic sensors within such event-driven approaches is proposed. With this aim, several topologies of such GMR sensors have been designed, fabricated and characterized. In addition, integrated circuit interfaces of a standard CMOS technology are also proposed. Their suitability for this approach is then demonstrated by means of Cadence IC simulations.