X. Gong, Ying Wu, Haiwen Xu, Kaizhen Han, L. Chua, W. Zou, T. Henry
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引用次数: 0
Abstract
Contact resistance R c in the source/drain (S/D) regions of field-effect transistors (FETs) has increased significantly due to the shrinkage of contact area accompanied with the scaling of device dimensions in the past decades [1] . For the state-of-art transistor technology, the contact area is around 10×10 nm 2 [2] . R c , inversely proportional to the effective contact area, is the main parasitic resistance that limits the on-state current and switching speed of the device in the leading technology. To alleviate the impact of R c , an ultralow specific contact resistivity ρ c of less than 10 −9 Ω-cm 2 is required [3] .