Power consumption in transistor networks versus in standard cells

Abstract

Optimization of circuits to reduce power consumption is more and more important. Techniques to reduce power at architectural level are not sufficient to minimize the impact of power consumption in modern designs, using nano CMOS technologies. Classical standard cells methodology is widely used in digital designs. However it is far away of power optimization at physical design level. It is becoming necessary the establishment of a new physical design methodology to improve power reduction, mainly due to the leakage power increase. It is needed a methodology to allow the automatic generation of the layout of any logic function. The method should also optimize the circuit as much as possible. Considering this, the paper is focused in showing that the use of transistors networks gives a better solution in terms of power and delay than the traditional approach of using predesigned cells available in commercial standard cell libraries. The presented comparisons show an average reduction of 74% in leakage power and 21% in delay.