A 1-V, 1.4-2.5 GHz Charge-Pump-Less PLL for a Phase Interpolator Based CDR

Abstract

A 1.4-2.5 GHz charge-pump-less phase locked loop (PLL) and a linear phase interpolator (PI) with dummy cells to enhance linearity are implemented in 0.13-mum CMOS. The loop filter with RC integrators and a V-I converter are proposed for achieving wide frequency range and high linearity in the voltage controlled oscillator (VCO) under a low supply voltage. The measured RMS and peak-peak jitters are 4.05 ps and 28.18 ps at 2 GHz, respectively. The measured DNL and INL of the PI are 0.27 LSB and 0.68 LSB, respectively.