A compact DC model for dual-independent-gate FinFETs

Abstract

To: (i) reduce the power consumption in digital integrated circuits, (ii) increase the transistor trans-conductance generation efficiency in analog circuits, and (iii) attain a very sensitive nonlinear response to RF, transistors exhibiting very steep room-temperature subthreshold slope (SS) are required. The subthreshold slope of conventional MOSFETs is limited to >60mV/dec due to their current turn-on mechanism being thermionic emission. During the last decade, several emerging transistor concepts, based on alternative current transport mechanisms, have been proposed so to overcome this fundamental limitation. For instance, Tunnel FETs (TFETs) have emerged as one of the most attractive alternatives to traditional MOSFETs, with experimental demonstrations of SS below 30 mV/dec, due to the current turn-on mechanism in such devices being band-to-band tunneling. In this context, dual-independent-gate (DIG) FinFETs have been also demonstrated capable of achieving a very steep subthreshold slope [1, 2]. The reason behind this super steep slope is a positive feedback induced by weak impact ionization in the device. Experimental demonstrations of DIG FinFETs have shown SS of 3.4 mV/dec at room-temperature over 5 decades of current swing [1, 2]. In this paper, we discuss a simple, closed-form analytic model for the current-voltage characteristics of DIG FinFETs, which can be of interest for many applications including circuit-design and application oriented device performance evaluation.