Defect and fault tolerant cell architecture for feasible nanoelectronic designs

Abstract

Several nanoelectronic devices have been already proved. However, no architecture which makes use of them provides a feasible opportunity to build a medium/large system. Nanoarchitecture proposals only solve a small part or the problems needed to achieve a real design. In this paper we review the two main approaches to nanoarchitectures showing some of their shortcomings. Taking into account these limitations, we propose and analyze a cell architecture that overcomes most of them. This architecture combines nanodevices with MOS technology to define a new architecture able to take advantage of both of them in a structure feasible for practical implementation. Using the cell structure we build 2 and 3-input NAND gates showing their error probabilities. Finally, we outline a method to further improve the structure's tolerance by taking advantage of interferences among nanodevices