Test generation for analog circuits using partial numerical simulation

Abstract

In this paper, we present a novel test generation strategy based on partial numerical fault simulation. Existing fault-based test generation methodologies for analog circuits are based on accurate but expensive fault simulation. In the proposed methodology, fault simulation is terminated before convergence for reasons of simulation speed. The relative fitness of various input stimuli is evaluated based on the results of this partial numerical simulation. A comparison of this new methodology with existing accurate fault simulation based test generation methods, shows up to 15 times speed-up in test generation.