{"title":"Templates for synthesis from VHDL","authors":"Z. Navabi, J. Spillane","doi":"10.1109/ASIC.1990.186201","DOIUrl":null,"url":null,"abstract":"Two templates for synthesizable VHDL description styles and their corresponding hardware are presented. One style is at the dataflow level with an explicit clocking scheme. The other uses behavioral VHDL for describing functionality and dataflow for architectural specification.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1990.186201","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
Two templates for synthesizable VHDL description styles and their corresponding hardware are presented. One style is at the dataflow level with an explicit clocking scheme. The other uses behavioral VHDL for describing functionality and dataflow for architectural specification.<>
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