Low power/high speed optimization approaches of MISTY algorithm

Abstract

This paper presents two approaches targeting the reduction of power dissipation, the delay time and silicon area of S7 and S9 blocks of MISTY1 encryption algorithm. The essential part of both approaches is to reduce the number of logic gates (XOR and AND gates) used in S7 and S9 blocks ciphers. The first approach reduces the number of logic gates by applying Boolean Algebra rules and simplifications, while the second approach removes the redundant logic gates which form the S7 and S9 blocks ciphers. The first approach reduced the dynamic power dissipation and the silicon area by 21.7%, 25.3%, respectively, while the throughput enhanced by 21.1%. The second approach reduced the dynamic power dissipation and the silicon area by 27%, 31.7%, respectively, while the throughput enhanced by 3.8%. As a result, the proposed approaches could be fit for next generation of handheld and portable devices.