A Comparator Speed Enhancement Technique for Near- and Sub-Threshold ADCs

Abstract

This paper presents a comparator speed enhancement technique for successive approximation register (SAR) analog-to-digital converter (ADC) under near- and sub-threshold supply voltages. The proposed delayed cross-coupling comparator effectively improves the speed of the comparator while maintaining a good noise performance. This work has been proved by a 350mV 8bit 12MS/s SAR ADC designed in a 65nm CMOS technology. The post-layout simulation shows that the ADC achieves SNDR of 48.83dB and SFDR of 63.72dB. The overall power consumption is $6.71\mu \mathrm{W}$, resulting in a figure-of-merit (FoM) of 2.47 fJ/convertion-step. The simulation results present that the proposed comparator speed enhancement technique significantly improves the sampling rate of the ADC under near- and sub-threshold supply voltages.