Time-Multiplexed Flash ADC for Deep Neural Network Analog in-Memory Computing

Abstract

This paper presents a Flash A/D converter to be integrated at the periphery of mixed-signal computing memories for convolutional neural networks. We investigate the feasibility of a true time-multiplexing, which allows to greatly relax the ADC requirements of area and aspect ratio, without sacrificing the data throughput of the memory array. The ADC, based on a strong-arm latched comparator combining built-in reference generation, body bias, and offset calibration, exhibits 29.8-dB SNDR at 3.2 GS/s with 1.5-mW power consumption, and a silicon area of $900\ \mu\mathrm{m}^{2}$. Integrated with the memory array, the converter enables up to 32-to-1 column multiplexing with 20 ns of A/D conversion latency.