K. Yamaguchi, H. Nanbu, K. Kanetani, N. Homma, T. Nakamura, K. Ohhata, A. Uchida, K. Ogiue
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引用次数: 8
Abstract
An experimental soft-error immune 64-kb 3-ns emitter couple logic (ECL) random access memory (RAM) has been developed. Its key factors are: a soft-error immune memory cell, an upward transistor decoder, a Darlington word driver with advanced discharge circuits, and 0.8 mu m SICOS technology. To reduce the memory cell size, double-layer polysilicon is used for high and low load-resistor. These double layers of polysilicon are essential in realizing the memory cell size of 498 mu m/sup 2/.<>
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