{"title":"Building-in reliability, application to bipolar/CMOS/DMOS technology","authors":"X. Gagnard, O. Bonnaud","doi":"10.1109/IPFA.2002.1025635","DOIUrl":null,"url":null,"abstract":"A permanent goal for an integrated circuit foundry is the improvement of reliability to avoid failures during component life. Ideally, the components should be tested in the mission profile conditions for the total duration. Specific tests must be accelerated to reduce the measurement time without creating new degradations, but also to detect the true defect or its origins. We have developed a building-in reliability approach for a front-end. The wafer level reliability (WLR) is set-up by electrical or physical tests during or at the end of the process, to eliminate defects directly at their origins. Our study concerned mainly a bipolar/CMOS/DMOS (BCD) technology.","PeriodicalId":328714,"journal":{"name":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.2002.1025635","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A permanent goal for an integrated circuit foundry is the improvement of reliability to avoid failures during component life. Ideally, the components should be tested in the mission profile conditions for the total duration. Specific tests must be accelerated to reduce the measurement time without creating new degradations, but also to detect the true defect or its origins. We have developed a building-in reliability approach for a front-end. The wafer level reliability (WLR) is set-up by electrical or physical tests during or at the end of the process, to eliminate defects directly at their origins. Our study concerned mainly a bipolar/CMOS/DMOS (BCD) technology.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
