Reduced circuit modeling of mother board and package for a system power delivery analysis

Abstract

An algorithm for generating a reduced circuit model of a multi-port power delivery network (PDN) is proposed. Compared to a macromodeling method, this algorithm creates a reduced model which is much simpler and uses only a small portion of CPU time during transient analysis for system power delivery. The algorithm uses an expanded Pi-network to easily visualize the internal branch connection impedances within the PDN. The reduced models efficiently replace the existing macromodels for the motherboard and package in a system analysis where the decoupling capacitors complement the band-limited nature of the reduced model.