A 14-bit 500-MS/s SHA-less Pipelined ADC in 65nm CMOS Technology for Wireless Receiver

Abstract

A 14-bit 500-MS/s SHA-less pipelined Analog-to-Digital Converter (ADC) for receiver application is fabricated on a 65 nm CMOS relying on correlation-based background calibrations to correct the inter-stage gain and settling errors. In order to suppress the non-linearity caused by inter-stage gain error due to insufficient amplifier gain, a new dithering technique is employed on the residual transfer function. In addition, the comparators in all stages are trimmed digitally to minimize their offset and further improve the linearity. The measured signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR) are 67 dB and 88 dB after calibration at 350 MHz input signal. The ADC occupies an active area of 3 mm2 and consumes a total power of 0.9 W from 1.3 V and 2.0 V supplies.