Co-integrated dual strained channels on fully depleted sSDOI CMOSFETs with HfO/sub 2//TiN gate stack down to 15nm gate length

Abstract

We report an original dual channel fully depleted CMOSFET architecture on insulator (DCOI) co-integrating strained-Si (nMOS) and strained-Si/sub 0.6/Ge/sub 0.4/ (pMOS) with HfO/sub 2//TiN gate stacks down to 15nm gate length. We demonstrate for the first time an I/sub ON/ improvement for short channel SOI of 10% at 35nm gate length (25% at 75nm, 100% on long channels) for both n- and p-MOSFETs and a more than 3 decades gate leakage reduction compared to a SiO/sub 2/ dielectric. Meanwhile, thanks to the dual channel engineering, a threshold voltage adjustment is performed with a mid gap single metal gate suitable for high performance (HP) CMOS.