A PELOX isolated sub-0.5 micron thin-film SOI technology

P. Gilbert, S. Sun
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引用次数: 1

Abstract

The integration of Poly-Encapsulated LOCOS (PELOX) into a high performance sub-0.5 /spl mu/m thin-film SOI technology is described. The 700 /spl Aring/ (per side) bird's beak encroachment of PELOX eliminates the need for a field implant and results in a significant reduction of the MOSFET narrow width effect. Partially-depleted N+/P+ dual poly gate MOSFET's with 70 /spl Aring/ Tox and 0.35 /spl mu/m Lpoly were fabricated with /spl les/1 /spl mu/m active/isolation pitch. A 40% reduction in power-delay product, compared to bulk CMOS, is achieved with a CMOS ring oscillator propagation-delay of 51 psec at 2 V supply voltage.
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一种PELOX隔离的亚0.5微米薄膜SOI技术
描述了将聚封装LOCOS (PELOX)集成到性能低于0.5 /spl μ l /m的薄膜SOI技术中。PELOX的700 /spl孔径/(每侧)鸟嘴侵蚀消除了现场植入的需要,并显著降低了MOSFET窄宽度效应。采用1 /spl /1 /spl /1 /spl /m有源/隔离节距,制备了70 /spl / Tox和0.35 /spl μ m Lpoly的N+/P+部分耗尽双多极MOSFET。在2v电源电压下,CMOS环形振荡器的传播延迟为51 psec,与本体CMOS相比,功率延迟产品减少了40%。
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Semiconductor CIM system, innovation toward the year 2000 CVD SiN/sub X/ anti-reflective coating for sub-0.5 /spl mu/m lithography Advantage of small geometry silicon MOSFETs for high-frequency analog applications under low power supply voltage of 0.5 V The influence of oxygen at epitaxial Si/Si substrate interface for 0.1 /spl mu/m epitaxial Si channel N-MOSFETs grown by UHV-CVD High-current, small parasitic capacitance MOS FET on a poly-Si interlayered (PSI: /spl Psi/) SOI wafer
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