F. Allibert, K. Cheng, M. Vinet, W. Schwarzenbach, A. Khakifirooz, L. Ecarnot, B. Nguyen, B. Doris
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引用次数: 3
Abstract
We assessed the performance of planar fully-depleted transistors built on sSOI wafers by comparing them to devices fabricated with the same process on SOI. A 23% increase in device performance was demonstrated, while maintaining at least as good device electrostatics and matching as SOI.
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