Interconnect Design and Technology Optimization for Conventional and Emerging Nanoscale Devices: A Physical Design Perspective

Abstract

Interconnect parasitics severely limit the performance and power dissipation in modern circuits at the advanced process technology nodes. Hence, device-level advances must be complemented with appropriate interconnect technology and design innovations for effective enablement at the circuit and system levels. This paper highlights the impact of device technologies on the optimal interconnect design and circuit-level metrics. The FinFET and Tunnel-FETs are studied by building fully placed-and-routed physical designs. The impact of device and interconnect technology co-optimization on circuit performance, power, and variability is shown for a range of emerging devices.