Design of Press-Pack Packaging for High Voltage SiC DSRD Stack

Abstract

SiC drift step recovery diode (DSRD) could be applied in the field of nanosecond high-power pulses. There is a demand for packaging for higher voltage and higher speed SiC DSRD. This paper proposes a stacked structure consisting of several high voltage SiC DSRD chips connected in series by rigid press-pack packaging. Finite element simulations performed to investigate the parasitic parameter, thermal performance in the packaging show that the packaging gets low parasitic inductance of about 3.5 nH and favorable heat dissipation capability. For the high-voltage SiC DSRD press-pack modules, the high field concentration around the DSRD chips is more critical. The objective is to build uniform electric field by structural optimization. A methodology to optimize the length of the metal conductive layer inside the packaging is proposed. Finally, the impact of the length on the electric field distribution is investigated quantitatively with Maxwell simulations. The electric field optimization brought by the platform reduces the maximum electric field intensity by 16%, which provides a packaging design reference for the upcoming high-voltage SiC DSRD devices.