{"title":"Ground bounce considerations in DC parametric test generation using boundary scan","authors":"Amitava Majumdar, M. Komoda, Tim Ayres","doi":"10.1109/VTEST.1998.670853","DOIUrl":null,"url":null,"abstract":"The problem of generating DC parametric test patterns while reducing ground bounce is considered. A clear tradeoff is identified between test time and the amount of ground bounce. An algorithm generating input DC tests with minimum ground bounce is proposed. Furthermore, we propose algorithms for reducing ground bounce for output DC tests under test time constraints based on the amount of information available. Experimental results prove that these algorithms not only reduce ground bounce but also keep test time within reasonable limits.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTEST.1998.670853","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
The problem of generating DC parametric test patterns while reducing ground bounce is considered. A clear tradeoff is identified between test time and the amount of ground bounce. An algorithm generating input DC tests with minimum ground bounce is proposed. Furthermore, we propose algorithms for reducing ground bounce for output DC tests under test time constraints based on the amount of information available. Experimental results prove that these algorithms not only reduce ground bounce but also keep test time within reasonable limits.