A low-phase noise 12 GHz digitally controlled oscillator in 65 nm CMOS for a FMCW radar frequency synthesizer

Abstract

This paper presents a power-efficient low-phase noise digitally controlled oscillator (DCO) implemented in a 65 nm CMOS technology. The DCO is designed for a 12 GHz frequency synthesizer covering up to 1GHz of frequency sweep range demanded by the frequency modulated continuous wave (FMCW) radar. The realized DCO circuit is designed to meet the stringent phase noise specifications of less than −110dBc/Hz @ 1MHz, required by the high resolution industrial indoor secondary FMCW radar system. The 12 GHz frequency synthesizer is based on a fractional-N all digital phased looked-loop (ADPLL) achieving a tuning range of 18.8 % using an 8-bit capacitive DAC array. This way, the DCO reliably covers up to 1GHz of frequency sweep range plus PVT variations. The low-power design achieves a phase noise performance of better than −112.3 dBc/Hz at a 1MHz offset. In summary, the DCO achieves a best in class figure of merit (FOMT) value of −186.7 dB with largest tuning range of 18.8 %, while only consuming 16.4 mW.