Designs of High-Speed Triple-Node-Upset Hardened Latch Based on Dual-Modular-Redundancy

Abstract

The development of modern process CMOS integrated circuits has reduced the feature sizes and thus the reliability of the chip continuously. First, this paper proposed two kinds of single-node upset self-recovery feedback loops with low overhead. One is called P-RFL which is composed of P-type complementary element (CP) and Clocked CP (C 2 P), and the other is called N-RFL which is composed of N-type complementary element (CN) and Clocked CN (C 2 N). Second, in order to fully tolerate triple-node upsets (TNUs), this paper presents three TNU-hardened latches: C 2 P-C 2 N, DMR-C 2 P and DMR-C 2 N. Using the blocking ability of the C-element, the outputs of two RFLs are connected to the C-element array. Therefore, when any three nodes upset at the same time, the transient pulse propagates inside the latch step by step, and disappears after being blocked by the C-element, ensuring that the TNU-hardened latches can restore to the correct logic state. HSPICE simulations show that all the three proposed latches achieve lower power, delay and APDP, compared with other six TNU-hardened latches. DMR-C 2 N achieves the lowest power, delay and APDP. In addition, the PVT variations analysis show that three proposed TNU-hardened latches are less sensitive to the variations of process, voltage and temperature.