SPC-Indexed Indirect Branch Hardware Cache Redirecting Technique in Binary Translation

IF 0.9 4区 工程技术 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Journal of Circuits Systems and Computers Pub Date : 2024-03-28 DOI:10.1142/s0218126624502426
Chunqiang Li, Zhiwei Liu, Yunhai Shang, Lenian He, Xiaolang Yan
{"title":"SPC-Indexed Indirect Branch Hardware Cache Redirecting Technique in Binary Translation","authors":"Chunqiang Li, Zhiwei Liu, Yunhai Shang, Lenian He, Xiaolang Yan","doi":"10.1142/s0218126624502426","DOIUrl":null,"url":null,"abstract":"<p>In the domain of process virtual machine (PVM) binary translation, the difference in address space layout between the guest program and the translated program requires the recalculation of jump instruction targets, resulting in suboptimal execution efficiency. This paper presents a novel method called SPC-Indexed Indirect Branch Hardware Cache Redirecting (SPCIC) technique. SPCIC utilizes specialized branch instruction to represent indirect branches from guest programs while frequently-used target addresses are cached in a customized hardware mapping table. When translating an indirect branch, SPCIC queries the jump target cache first to achieve a fast redirection unless the destination address is not cached. Besides, SPCIC merely falls back to the software-based remapping approach when the query fails, improving the translation efficiency to the greatest extent. SPCIC is implemented on the QEMU platform to accelerate the translation of ARM payloads into RISC-V. Experiments are carried on SPEC2006 to demonstrate the effectiveness of SPCIC for reducing the runtime overhead of indirect branch translation. The experimental results indicate up to 11% average improvement and 35% maximum improvement are obtained on the selected benchmark.</p>","PeriodicalId":54866,"journal":{"name":"Journal of Circuits Systems and Computers","volume":"45 1","pages":""},"PeriodicalIF":0.9000,"publicationDate":"2024-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Circuits Systems and Computers","FirstCategoryId":"5","ListUrlMain":"https://doi.org/10.1142/s0218126624502426","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
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Abstract

In the domain of process virtual machine (PVM) binary translation, the difference in address space layout between the guest program and the translated program requires the recalculation of jump instruction targets, resulting in suboptimal execution efficiency. This paper presents a novel method called SPC-Indexed Indirect Branch Hardware Cache Redirecting (SPCIC) technique. SPCIC utilizes specialized branch instruction to represent indirect branches from guest programs while frequently-used target addresses are cached in a customized hardware mapping table. When translating an indirect branch, SPCIC queries the jump target cache first to achieve a fast redirection unless the destination address is not cached. Besides, SPCIC merely falls back to the software-based remapping approach when the query fails, improving the translation efficiency to the greatest extent. SPCIC is implemented on the QEMU platform to accelerate the translation of ARM payloads into RISC-V. Experiments are carried on SPEC2006 to demonstrate the effectiveness of SPCIC for reducing the runtime overhead of indirect branch translation. The experimental results indicate up to 11% average improvement and 35% maximum improvement are obtained on the selected benchmark.

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二进制转换中的 SPC 索引间接分支硬件缓存重定向技术
在进程虚拟机(PVM)二进制转换领域,由于客程序和被转换程序的地址空间布局不同,需要重新计算跳转指令目标,从而导致执行效率不理想。本文提出了一种名为 SPC-Indexed Indirect Branch Hardware Cache Redirecting(SPCIC)技术的新方法。SPCIC 利用专门的分支指令来表示访客程序的间接分支,而常用的目标地址则缓存在定制的硬件映射表中。在转换间接分支时,除非目标地址没有缓存,否则 SPCIC 会首先查询跳转目标缓存,以实现快速重定向。此外,当查询失败时,SPCIC 只会退回到基于软件的重映射方法,从而最大程度地提高了转换效率。SPCIC 是在 QEMU 平台上实现的,用于加速 ARM 有效载荷到 RISC-V 的转换。在 SPEC2006 上进行了实验,以证明 SPCIC 在减少间接分支转换的运行时开销方面的有效性。实验结果表明,在所选基准上,平均改进幅度达 11%,最大改进幅度达 35%。
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来源期刊
Journal of Circuits Systems and Computers
Journal of Circuits Systems and Computers 工程技术-工程:电子与电气
CiteScore
2.80
自引率
26.70%
发文量
350
审稿时长
5.4 months
期刊介绍: Journal of Circuits, Systems, and Computers covers a wide scope, ranging from mathematical foundations to practical engineering design in the general areas of circuits, systems, and computers with focus on their circuit aspects. Although primary emphasis will be on research papers, survey, expository and tutorial papers are also welcome. The journal consists of two sections: Papers - Contributions in this section may be of a research or tutorial nature. Research papers must be original and must not duplicate descriptions or derivations available elsewhere. The author should limit paper length whenever this can be done without impairing quality. Letters - This section provides a vehicle for speedy publication of new results and information of current interest in circuits, systems, and computers. Focus will be directed to practical design- and applications-oriented contributions, but publication in this section will not be restricted to this material. These letters are to concentrate on reporting the results obtained, their significance and the conclusions, while including only the minimum of supporting details required to understand the contribution. Publication of a manuscript in this manner does not preclude a later publication with a fully developed version.
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