HLS Implementation of a Building Cube Stencil Computation Framework for an FPGA Accelerator

Abstract

FPGAs are promising energy-efficient accelerators for computing-intensive applications such as electromagnetic field simulations, which are also important tasks for consumer product design. Especially, stencil computation, which is a commonly-used computing pattern for scientific and engineering simulations, is known to have a high degree of affinity with FPGAs. In practical simulations, data reduction methods, such as the building cube method (BCM), are often utilized to balance computation accuracy and speed. However, such techniques tend to introduce irregular memory access patterns, making it a tough task for application programmers to implement efficient memory access hardware units in FPGAs. In this paper, we propose a design framework for stencil computation with BCM, enabling application programmers to focus on algorithm implementation without being aware of memory access optimization. We implement the framework on an Intel FPGA PAC D5005 platform, to evaluate its effectiveness in terms of resource utilization, execution time, and throughput. As for resource utilization, it was confirmed that the area overhead of the proposed BCM framework is small enough, leaving sufficient resource space for user applications. The performance evaluation results revealed that the measured throughput of the BCM framework deteriorated by more than 90% compared to non-BCM execution due to irregular memory access patterns. However, since the number of cells to be computed in BCM is significantly reduced, the final computation speed was improved by up to 28 times, indicating that the reduction in the throughput is acceptable.