Global RC Interconnects with ADL Buffers for Low-Power Applications

Abstract

Interconnects are an essential requirement for any circuit completion. They are utilised to connect two or more blocks, yet when creating a circuit, certain problems have been observed. Scaling back technology is one such problem. With technology scaled down their aspects change which can straightforwardly affect the circuit boundaries. Because of this, the time constant and power consumption in the interconnect circuits has increased. Certain wire (RC) models and techniques have previously been characterized to control these performance parameters however in this paper, authors have proposed a new interconnect structure with a buffer insertion technique using adiabatic dynamic logic (ADL). To optimise power, a Schmitt trigger is inserted as a buffer between lengthy interconnect circuits utilising an energy-recovery mechanism. The TSPICE tool is used to model and simulate the entire circuit. The suggested model's performance is compared to that of other cutting-edge methods. The complete circuits are modelled and simulated using the SPICE tool. A performance comparison is done between the existing model and the proposed model.