Su Hyun Kim, Mingoo Kim, Ji Hwan Lee, Kihwan Kim, Joon Seok Park, Jun Hyung Lim, Saeroonter Oh
{"title":"Optimizing Length Scalability of InGaZnO Thin-Film Transistors through Lateral Carrier Profile Engineering and Negative ΔL Extension Structure","authors":"Su Hyun Kim, Mingoo Kim, Ji Hwan Lee, Kihwan Kim, Joon Seok Park, Jun Hyung Lim, Saeroonter Oh","doi":"10.1002/aelm.202400012","DOIUrl":null,"url":null,"abstract":"<p>The lateral carrier profile of amorphous indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) plays a significant role in determining the effective channel length (<i>L</i><sub>eff</sub>) and length scalability even when the physical gate length (<i>L</i><sub>g</sub>) is the same. Especially, devices with high carrier concentration that have a high mobility of 14.54 cm<sup>2</sup> V·s<sup>−1</sup> suffer from severe short channel effects at <i>L</i><sub>g</sub> = 1 µm due to the reduced <i>L</i><sub>eff</sub>. The current work proposes a systematic methodology for optimizing length scalability for a given <i>L</i><sub>g</sub> that involves engineering of the lateral carrier profile. Unique lateral carrier profiles are extracted using contour maps of Δ<i>L</i> and <i>R</i><sub>SD</sub> as a function of carrier profile parameters, and they are validated by comparing the measured <i>L</i><sub>eff</sub>, drain-to-source resistance, and current-voltage characteristics with the results of simulations using the extracted carrier profiles. Further, to overcome the trade-off between enhanced mobility and degraded <i>V</i><sub>T</sub> roll-off that occurs with increasing carrier concentration, an IGZO TFT with gate-insulator shoulders is fabricated to structurally form negative Δ<i>L</i> and physically increase <i>L</i><sub>eff</sub>, while also obtaining a high carrier concentration, ultimately achieving both optimal electrical performance, with mobility of 17.50 cm<sup>2</sup> V·s<sup>−1</sup>, and complete control of the electrostatic integrity of the gate.</p>","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"10 10","pages":""},"PeriodicalIF":5.3000,"publicationDate":"2024-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.202400012","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Advanced Electronic Materials","FirstCategoryId":"88","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1002/aelm.202400012","RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"MATERIALS SCIENCE, MULTIDISCIPLINARY","Score":null,"Total":0}
引用次数: 0
Abstract
The lateral carrier profile of amorphous indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) plays a significant role in determining the effective channel length (Leff) and length scalability even when the physical gate length (Lg) is the same. Especially, devices with high carrier concentration that have a high mobility of 14.54 cm2 V·s−1 suffer from severe short channel effects at Lg = 1 µm due to the reduced Leff. The current work proposes a systematic methodology for optimizing length scalability for a given Lg that involves engineering of the lateral carrier profile. Unique lateral carrier profiles are extracted using contour maps of ΔL and RSD as a function of carrier profile parameters, and they are validated by comparing the measured Leff, drain-to-source resistance, and current-voltage characteristics with the results of simulations using the extracted carrier profiles. Further, to overcome the trade-off between enhanced mobility and degraded VT roll-off that occurs with increasing carrier concentration, an IGZO TFT with gate-insulator shoulders is fabricated to structurally form negative ΔL and physically increase Leff, while also obtaining a high carrier concentration, ultimately achieving both optimal electrical performance, with mobility of 17.50 cm2 V·s−1, and complete control of the electrostatic integrity of the gate.
期刊介绍:
Advanced Electronic Materials is an interdisciplinary forum for peer-reviewed, high-quality, high-impact research in the fields of materials science, physics, and engineering of electronic and magnetic materials. It includes research on physics and physical properties of electronic and magnetic materials, spintronics, electronics, device physics and engineering, micro- and nano-electromechanical systems, and organic electronics, in addition to fundamental research.