A 167-$\mu$W 71.7-dB SFDR 2.4-GHz BLE Receiver Using a Passive Quadrature Front End, a Double-Sided Double-Balanced Cascaded Mixer, and a Dual-Transformer-Coupled Class-D VCO

IF 4.6 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Journal of Solid-state Circuits Pub Date : 2024-10-01 DOI:10.1109/jssc.2024.3462093
Haijun Shao, Rui P. Martins, Pui-In Mak
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使用无源正交前端、双面双平衡级联混频器和双变压器耦合 D 类 VCO 的 167-$\mu$W 71.7-dB SFDR 2.4-GHz BLE 接收器
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来源期刊
IEEE Journal of Solid-state Circuits
IEEE Journal of Solid-state Circuits 工程技术-工程:电子与电气
CiteScore
11.00
自引率
20.40%
发文量
351
审稿时长
3-6 weeks
期刊介绍: The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
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