Knowledge transferring framework for cell library characterization

Abstract

To evaluate digital circuit performance across PVT (process, voltage, and temperature) corners, standard cell library characterization requires costly simulations. Leveraging machine learning (ML) can improve the efficiency of this process. However, existing ML-based methods for cell library characterization often neglect the knowledge embedded across different timing arcs, leading to the need for extensive training data. In this paper, we propose a transfer learning (TL) framework to enhance timing characterization across multiple timing arcs. By quantifying the similarity among training tasks in the cell library using a fine-grained metric, our method enables rapid and accurate cell delay predictions through pre-training knowledge. Compared to conventional ML approaches, our TL framework improves both prediction accuracy and efficiency. Experimental results on 45 nm MOSFET and 14 nm FINFET technologies show significant error reductions of up to 80% and 67%, respectively.