Yingchun Lu , Changlong Cao , Yang Liu , Huaguo Liang , Liang Yao , Lixiang Ma
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引用次数: 0
Abstract
True random number generator is a crucial hardware system component that is widely used in the fields of cryptographic communication, key generation, statistical simulation, and secure authentication. However, the related TRNG suffers from low throughput and high resource overhead due to relying on a single entropy source. To address this issue, a TRNG circuit implementation scheme based on a MUX-XOR gate cell (MX-cell) is proposed, which uses the switching characteristics of the MUX and the XOR gate to generate metastability and jitter to develop a hybrid entropy source. It further enables the dynamic superposition of entropy sources under prescribed conditions, which improves the TRNG throughput while reducing the resource overhead. The proposed TRNG is implemented on Xilinx Artix-7 and Kintex-7 FPGAs with automatic placement and routing, passing NIST, AIS-31, TESTU01 statistical test suites and a series of other performance tests without post-processing. The experimental results reveal that the suggested design consumes only 19 LUTs, 8 DFFs, and 4 MUXs to provide random numbers with up to 380 Mbps throughput, which demonstrates highly efficient resource utilization compared to advanced published TRNGs.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.