JoBiS: Joint capacitance and inductance bit stuffing CAC for interposer based multi-chip Deep Learning Accelerator

Abstract

Interposer-based multi-chip Deep Learning Accelerator (DLA) profoundly influences the design of artificial intelligence (AI) hardware. However, data transmission over wires in Network-on-Chip (NoC)-based Deep Learning Accelerators (DLAs) encounters crosstalk faults as a major challenge. These faults arise due to mutual capacitance and inductance influences between adjacent wires of the NoCs. To address this issue, this paper introduces JoBiS, a bit-stuffing algorithm that takes into account both capacitance and inductance coupling effects. JoBiS aims to prevent the occurrence of the worst delay transitions in inductance coupling, such as 00000$\to 11111,11111\to$00000, and 00-00$\to$11-11, as well as in capacitive coupling, including 11-11$\to$00-00, 01010$\to$10101, and 10101$\to$01010, in a 5-bit wire model. This is achieved through a simple and low-power algorithm. To reduce delay and area overhead in large buses, a bus partitioning-based CAC called JoBiS is proposed. The simulation results indicate that the power consumption and delay are significantly improved compared to other methods. On average, JoBiS reduces power consumption and critical path delay by 83% and 70%, respectively, across various bus widths.