Capacitance Effects of Nanopore Chips on Ionic Current Modulation and Noise Characteristics.

Abstract

Solid-state nanopores exhibit adjustable pore size, robust chemical and thermal stability, and compatibility with semiconductor fabrication, positioning them as versatile platforms for nanofluidic applications and single-molecule detection. However, their higher noise levels compared to biological nanopores hinder their sensitivity in detecting biomolecules such as DNA and proteins. Enhancing detection sensitivity requires an in-depth understanding of noise sources and strategies for noise reduction. Here, we construct an equivalent circuit model of solid-state nanopores and conduct corresponding experiments to evaluate how chip capacitance, salt concentration, applied voltage, and pore size influence ionic current noise. We find that chip capacitance is the dominant factor affecting ionic current noise, with minimal noise sensitivity to salt concentration below 0.1 M but pronounced increases above this threshold. The pH has little impact on noise, whereas higher applied voltages elevate noise at high salt concentrations. Introducing a SiO₂layer between SiN_xand Si significantly reduces chip capacitance; a 1000 nm SiO₂layer reduces capacitance to 7.9 pF, decreasing ionic current noise to 18.7 pA for a 2.2 nm nanopore in 1 M KCl at 40 μm membrane side length and 100 mV and 10 kHz sampling. This reduction in capacitance improves response time and measurement accuracy, marking a critical advancement for high-sensitivity applications of solid-state nanopores.