A 4H–SiC TMOS with triple trenches and high-K dielectric

Abstract

A novel 4H–SiC TMOS with triple trenches and high-K dielectric (TTHK-TMOS) is investigated. The main structural features include the triple trenches which are composed of a deep trench filled with high-K dielectric, a gate trench in the high-K dielectric deep trench and a source trench with P-type shielding layer. The high-K dielectric deep trench modulates the electric field and drift doping concentration, improves the breakdown voltage (BV) and reduces the specific on-resistance (R_on,sp). The gate trench with high-K dielectric forms the HKMG structure to modulate the channel current and alleviates the electric field concentration effect at the gate trench corner, reduces the highest gate oxide electric field intensity. The source trench together with the P-type shielding layer also relieves the electric field crowd to improve BV and reduce parasitic capacitance. Simulation results demonstrate that the TTHK-TMOS has a BV of 2501 V with a R_on,sp of only 1.17 mΩ cm², achieving a FOM of 5354 MW/cm². Compared to the conventional TMOS, TTHK-TMOS has increased its FOM by 226.7 %, lowered the V_TH by 52.6 %, and decreased the high frequency FOM by 23.1 % and 45.3 %, improving both static and dynamic performance.