Design and Implementation of a Low-cost AES Coprocessor Based on eSTT-MRAM IP

Abstract

In order to insure the security of message transmission between resource-constrained Internet of Things (IoT) devices, a low-cost hardware implementation of Advanced Encryption Standard (AES) coprocessor based on eSTT-MRAM (embedded spin-torque transfer magnetic random access memory) is presented in this paper. By reusing the round unit, the resource overhead of the design is reduced. In order to optimize the total area, a compact SubBytes module without look-up tables is presented by mapping the arithmetic operations on GF(28) to isomorphic field GF((24)2). The promising second-generation memory STT-MRAM is selected to store the key for each round (roundkey) to verify its coordination with security coprocessors. Simulation and synthesis results show that the proposed coprocessor can complete one encryption in 92/110/128 (AES-128/192/256) cycles consuming only 13.07K gates and 28µW at 13.56MHz and 1.2V.