Low power transformation of datapath architectures with cyclic SFGs

M. Wróblewski, S. Simon, J. Nossek
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引用次数: 1

Abstract

Datapath architectures exhibit a large amount of undesired switching (glitches) which does not contribute to the functionality but leads to increased power consumption. While glitch propagation can be effectively reduced by pipelining circuits with acyclic SFGs, this technique is not directly applicable if the circuit contains loops. The paper addresses this problem and discusses a methodology for reducing switching activity in recursive circuits. Simulation results of a few example circuits are given.
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循环SFGs数据路径架构的低功耗转换
数据路径架构表现出大量不希望的切换(小故障),这对功能没有贡献,但会导致功耗增加。虽然使用无环SFGs的流水线电路可以有效地减少故障传播,但如果电路包含环路,则该技术不能直接应用。本文解决了这个问题,并讨论了一种在递归电路中减少开关活动的方法。给出了几个示例电路的仿真结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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