Pub Date : 2000-12-03DOI: 10.1109/ISCAS.2000.858694
C. Tseng, K. Teo, A. Cantoni
A new type of adaptive scheme was proposed recently for designing a deterministic envelope-constrained (EC) filter such that the generated sequence of filters converges to the optimum filter. Previous results at this level of generality linked convergence only to within a neighborhood of the optimum filter. Based on the adaptive scheme, two new theorems are established in a stochastic environment for which the adaptive EC filter converges in mean square sense and with probability one to the noiseless optimum filter for a fixed step-size and a decreasing sequence of step-sizes, respectively. Numerical examples involving pulse compression Barker-coded signal are studied for solving the EC filtering problem.
{"title":"Adaptive envelope-constrained filter design","authors":"C. Tseng, K. Teo, A. Cantoni","doi":"10.1109/ISCAS.2000.858694","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.858694","url":null,"abstract":"A new type of adaptive scheme was proposed recently for designing a deterministic envelope-constrained (EC) filter such that the generated sequence of filters converges to the optimum filter. Previous results at this level of generality linked convergence only to within a neighborhood of the optimum filter. Based on the adaptive scheme, two new theorems are established in a stochastic environment for which the adaptive EC filter converges in mean square sense and with probability one to the noiseless optimum filter for a fixed step-size and a decreasing sequence of step-sizes, respectively. Numerical examples involving pulse compression Barker-coded signal are studied for solving the EC filtering problem.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80434260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-03DOI: 10.1109/ISCAS.2000.857416
Andrew Béla Frigyik, G. Kolumbán
In addition to the stable fixed point which should be achieved under steady-state conditions, the sampling phase-locked loop (SPLL) implemented with a loop filter has another stable attractor in which an unwanted periodic solution, called false lock, develops in the loop. After the acquisition process, the SPLL either reaches the desired fixed point or gets into false lock, depending on the initial conditions. In every implemented circuit, the development of false lock has to be prevented. Although the false lock problem was reported earlier, an exact model to describe the behavior of SPLL in false lock has not yet been published. This paper propose a phenomenological model to explain why the false lock can develop and to describe the operation of SPLL in false lock.
{"title":"Phenomenological model of false lock in the sampling phase-locked loop","authors":"Andrew Béla Frigyik, G. Kolumbán","doi":"10.1109/ISCAS.2000.857416","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857416","url":null,"abstract":"In addition to the stable fixed point which should be achieved under steady-state conditions, the sampling phase-locked loop (SPLL) implemented with a loop filter has another stable attractor in which an unwanted periodic solution, called false lock, develops in the loop. After the acquisition process, the SPLL either reaches the desired fixed point or gets into false lock, depending on the initial conditions. In every implemented circuit, the development of false lock has to be prevented. Although the false lock problem was reported earlier, an exact model to describe the behavior of SPLL in false lock has not yet been published. This paper propose a phenomenological model to explain why the false lock can develop and to describe the operation of SPLL in false lock.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89785558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-12-03DOI: 10.1109/ISCAS.2000.858786
S. Emami, K. Wada, Shigetaka Tagaki, N. Fujii
A new architecture for class A CMOS current conveyor is proposed. The proposed circuit is free from the body effect and provides high performance in terms of input resistance and transfer gain errors. HSPICE simulation using 2 /spl mu/m process parameters also confirms the effectiveness of the proposed circuit.
{"title":"A novel class A CMOS current conveyor","authors":"S. Emami, K. Wada, Shigetaka Tagaki, N. Fujii","doi":"10.1109/ISCAS.2000.858786","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.858786","url":null,"abstract":"A new architecture for class A CMOS current conveyor is proposed. The proposed circuit is free from the body effect and provides high performance in terms of input resistance and transfer gain errors. HSPICE simulation using 2 /spl mu/m process parameters also confirms the effectiveness of the proposed circuit.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75661312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-12DOI: 10.1109/ISCAS.2000.857606
Bo-Ting Wang, J. B. Kuo
This paper reports a two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability. With a unique structure connecting the source terminal of an NMOS device in the SRAM cell to the write word line, this SRAM cell can be used to provide SBLSRWA capability for 1V two-port VLSI SRAM as verified by SPICE results.
{"title":"A novel two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability","authors":"Bo-Ting Wang, J. B. Kuo","doi":"10.1109/ISCAS.2000.857606","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857606","url":null,"abstract":"This paper reports a two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability. With a unique structure connecting the source terminal of an NMOS device in the SRAM cell to the write word line, this SRAM cell can be used to provide SBLSRWA capability for 1V two-port VLSI SRAM as verified by SPICE results.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85035851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857203
K. Pahlke, Lars Kroneberg, W. Mathis
A scheme of quantum state manipulation is presented to implement a new kind of CNOT-gate in a two stored ion arrangement. This type of quantum gate enables the designer of quantum algorithms to "send information into the phonon bus" controlled by the information stored in one of the ions. Some simulation results are given to show the dynamics of the system during the step by step implementation.
{"title":"A CNOT-gate implementation for information transfer by the phonon bus","authors":"K. Pahlke, Lars Kroneberg, W. Mathis","doi":"10.1109/ISCAS.2000.857203","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857203","url":null,"abstract":"A scheme of quantum state manipulation is presented to implement a new kind of CNOT-gate in a two stored ion arrangement. This type of quantum gate enables the designer of quantum algorithms to \"send information into the phonon bus\" controlled by the information stored in one of the ions. Some simulation results are given to show the dynamics of the system during the step by step implementation.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73663116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856298
B. Gou, A. Abur
This paper extends the results of our previous work presented in [see IEEE Trans. on Power Systems], to the problem of multiple measurement placement. The essential contribution of this work is based on the multiple rank updating of triangular factors, which are subsequently utilized in the state estimation solution following the measurement placement. Examples are used to illustrate the effectiveness of proposed method in placing measurements in typical power systems.
{"title":"An efficient method for multiple measurement placement in power networks","authors":"B. Gou, A. Abur","doi":"10.1109/ISCAS.2000.856298","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856298","url":null,"abstract":"This paper extends the results of our previous work presented in [see IEEE Trans. on Power Systems], to the problem of multiple measurement placement. The essential contribution of this work is based on the multiple rank updating of triangular factors, which are subsequently utilized in the state estimation solution following the measurement placement. Examples are used to illustrate the effectiveness of proposed method in placing measurements in typical power systems.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73842169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857064
R. Ubar, J. Raik, A. Morawiec
The paper addresses the problem of the cycle-based simulation performance of synchronous digital systems modeled by High-Level Decision Diagrams (DDs). A new class of DD representation, called Register-Oriented DDs (RODD) is introduced. The RODD model appears to be an efficient and compact representation of the system behavior for the high-level cycle simulation. In order to fully exploit the advantages of RODDs a new simulation algorithm, which is a combination of cycle-based forward event-driven and recursive back-tracing techniques is proposed. The characteristics of the simulation algorithms used to efficiently execute the evaluation of the DD network are discussed. Further the experimental results carried out on the real case examples demonstrating the gain in simulation performance of the proposed approach and a comparison of four cycle-based simulation algorithms are presented. Additionally, a comparison with the commercial event-driven and cycle-based HDL simulation tools is included.
{"title":"Back-tracing and event-driven techniques in high-level simulation with decision diagrams","authors":"R. Ubar, J. Raik, A. Morawiec","doi":"10.1109/ISCAS.2000.857064","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857064","url":null,"abstract":"The paper addresses the problem of the cycle-based simulation performance of synchronous digital systems modeled by High-Level Decision Diagrams (DDs). A new class of DD representation, called Register-Oriented DDs (RODD) is introduced. The RODD model appears to be an efficient and compact representation of the system behavior for the high-level cycle simulation. In order to fully exploit the advantages of RODDs a new simulation algorithm, which is a combination of cycle-based forward event-driven and recursive back-tracing techniques is proposed. The characteristics of the simulation algorithms used to efficiently execute the evaluation of the DD network are discussed. Further the experimental results carried out on the real case examples demonstrating the gain in simulation performance of the proposed approach and a comparison of four cycle-based simulation algorithms are presented. Additionally, a comparison with the commercial event-driven and cycle-based HDL simulation tools is included.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75211957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.858745
Chung-Sheng Li, J. R. Smith, R. Mohan, Yuan-Chi Chang, B. Topol, J. Hind, Yongcheng Li
As Internet information portals become prevalent for both Internet and Intranet, most existing Internet Application Server architectures are not scalable to support the large amount of personalization, customization and content adaptation required. We propose a framework to capture the information and content dissemination process. Furthermore, we propose a methodology to map this process to a distributed application server environment. By fully exploiting the intersections of user preference at multiple content processing stages, this new framework enables high hit ratio on processing, storage, and transmission of content and thus scales well to support a large number of clients.
{"title":"Distributed application service for Internet information portal","authors":"Chung-Sheng Li, J. R. Smith, R. Mohan, Yuan-Chi Chang, B. Topol, J. Hind, Yongcheng Li","doi":"10.1109/ISCAS.2000.858745","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.858745","url":null,"abstract":"As Internet information portals become prevalent for both Internet and Intranet, most existing Internet Application Server architectures are not scalable to support the large amount of personalization, customization and content adaptation required. We propose a framework to capture the information and content dissemination process. Furthermore, we propose a methodology to map this process to a distributed application server environment. By fully exploiting the intersections of user preference at multiple content processing stages, this new framework enables high hit ratio on processing, storage, and transmission of content and thus scales well to support a large number of clients.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75430708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857506
Jia-Ching Wang, Jhing-Fa Wang, Han-Chiang Chen
In this paper, we propose a low bit rate speech vocoder and its corresponding VLSI implementation. The vocoder exploits the interpolation property so that the fine quality in synthesized speech is obtained even though the bit rate is as low as 1.6 kbps. Two novel methods including pitch detection and LSP decoding which are suitable for VLSI implementation are also proposed. The heuristic pitch detection algorithm avoids the heavy computational load introduced by the traditional normalized autocorrelation method. The memory storing triangular function value is no longer needed after adopting the new LSP decoding process. The chip is designed with area effective feature and is suitable for stand alone application.
{"title":"Single chip implementation of the 1.6 kbps speech vocoder","authors":"Jia-Ching Wang, Jhing-Fa Wang, Han-Chiang Chen","doi":"10.1109/ISCAS.2000.857506","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857506","url":null,"abstract":"In this paper, we propose a low bit rate speech vocoder and its corresponding VLSI implementation. The vocoder exploits the interpolation property so that the fine quality in synthesized speech is obtained even though the bit rate is as low as 1.6 kbps. Two novel methods including pitch detection and LSP decoding which are suitable for VLSI implementation are also proposed. The heuristic pitch detection algorithm avoids the heavy computational load introduced by the traditional normalized autocorrelation method. The memory storing triangular function value is no longer needed after adopting the new LSP decoding process. The chip is designed with area effective feature and is suitable for stand alone application.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75431885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856311
Jae J. Chang, M. Brooke
The necessity of passive components in analog circuit design such as Clock Recovery Circuits (CRC) or Phase Locked Loops (PLL) has been a main barrier to overcome especially when using a standard digital CMOS process. In addition to lack of support of high quality passives in digital CMOS, use of passive devices causes problems with area, thermal noise of resistance, process variation, mismatch of capacitances, and inability to scalable designs. Consequently current high speed clock recovery circuits are implemented mostly in bipolar technology or other passive friendly technology. However, these technologies are not well-suited to the higher levels of integration needed for "systems on a chip". Also, current technology emphasis is shifting from increasing the operation speed of components to reducing their size, power consumption, and cost to eliminating the need for adjustment and trimming. These goals can be achieved by using fully passive component-free monolithic CMOS circuits. In this paper, we present a method for implementing a passive component filter which can be used in clock recovery circuit or PLLs.
{"title":"A clock extraction circuit using passive components-free filter in standard digital process","authors":"Jae J. Chang, M. Brooke","doi":"10.1109/ISCAS.2000.856311","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856311","url":null,"abstract":"The necessity of passive components in analog circuit design such as Clock Recovery Circuits (CRC) or Phase Locked Loops (PLL) has been a main barrier to overcome especially when using a standard digital CMOS process. In addition to lack of support of high quality passives in digital CMOS, use of passive devices causes problems with area, thermal noise of resistance, process variation, mismatch of capacitances, and inability to scalable designs. Consequently current high speed clock recovery circuits are implemented mostly in bipolar technology or other passive friendly technology. However, these technologies are not well-suited to the higher levels of integration needed for \"systems on a chip\". Also, current technology emphasis is shifting from increasing the operation speed of components to reducing their size, power consumption, and cost to eliminating the need for adjustment and trimming. These goals can be achieved by using fully passive component-free monolithic CMOS circuits. In this paper, we present a method for implementing a passive component filter which can be used in clock recovery circuit or PLLs.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75856043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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