A novel two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability

Abstract

This paper reports a two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability. With a unique structure connecting the source terminal of an NMOS device in the SRAM cell to the write word line, this SRAM cell can be used to provide SBLSRWA capability for 1V two-port VLSI SRAM as verified by SPICE results.