Phenomenological model of false lock in the sampling phase-locked loop

Abstract

In addition to the stable fixed point which should be achieved under steady-state conditions, the sampling phase-locked loop (SPLL) implemented with a loop filter has another stable attractor in which an unwanted periodic solution, called false lock, develops in the loop. After the acquisition process, the SPLL either reaches the desired fixed point or gets into false lock, depending on the initial conditions. In every implemented circuit, the development of false lock has to be prevented. Although the false lock problem was reported earlier, an exact model to describe the behavior of SPLL in false lock has not yet been published. This paper propose a phenomenological model to explain why the false lock can develop and to describe the operation of SPLL in false lock.