A 66 dB SNDR pipelined split-ADC using class-AB residue amplifier with analog gain correction

Md Shakil Akter, R. Sehgal, Frank M. L. van der Goes, K. Bult
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引用次数: 7

Abstract

This paper proposes a class-AB residue amplifier topology that significantly improves the power efficiency of residue amplification. Due to its inherent high linearity, the amplifier can be allowed to have a reduced settling to further enhance its power efficiency while still maintaining the required linearity performance. Moreover, it enables an efficient way of correcting gain errors in the analog domain by simply tuning the bias current, without requiring any additional analog power. The digital power for calibration also becomes negligible, since the detection of gain errors can be done digitally at a slow rate. The calibration of the prototype pipelined split-ADC in a 40nm CMOS reaches convergence in only 12×103 clock cycles. The ADC achieves more than 10.3b ENOB near Nyquist input up to 106 MS/s clock speed. At 53 MS/s clock with close to Nyquist-frequency input, the ADC demonstrates an SNDR and SFDR of 66 dB and 77.3 dB respectively while consuming 9 mW of power, of which the residue amplifiers consume only 0.83 mW.
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一个66db SNDR流水线分流adc,采用ab类剩余放大器和模拟增益校正
本文提出了一种ab类残馀放大器拓扑结构,显著提高了残馀放大的功率效率。由于其固有的高线性度,放大器可以允许有一个减少的沉降,以进一步提高其功率效率,同时仍然保持所需的线性性能。此外,它可以通过简单地调整偏置电流来有效地纠正模拟域中的增益误差,而不需要任何额外的模拟功率。校正的数字功率也变得可以忽略不计,因为增益误差的检测可以在一个缓慢的速率数字完成。在40nm CMOS中校准原型流水线分裂adc仅在12×103时钟周期内达到收敛。ADC在Nyquist输入附近实现超过103亿ENOB,时钟速度高达106 MS/s。在53 MS/s时钟和接近nyquist频率的输入下,ADC的SNDR和SFDR分别为66 dB和77.3 dB,功耗为9 mW,其中剩余放大器仅消耗0.83 mW。
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Theoretical analyses and modeling for nanoelectronics A 66 dB SNDR pipelined split-ADC using class-AB residue amplifier with analog gain correction Suppression of VCO pulling effects using even-harmonic quiet transmitting circuits A 6-bit 10-GS/s 63-mW 4x TI time-domain interpolating flash ADC in 65-nm CMOS A 0.01 mm2 fully-differential 2-stage amplifier with reference-free CMFB using an architecture-switching-scheme for bandwidth variation
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