A 6-bit 10-GS/s 63-mW 4x TI time-domain interpolating flash ADC in 65-nm CMOS

Dong-Ryeol Oh, Jong-In Kim, M. Seo, Jin-Gwang Kim, S. Ryu
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引用次数: 14

Abstract

A 6-b 4x time-interleaved (TI) time-domain interpolating flash ADC is presented for high-speed applications. The dynamic-amplifier-structured voltage-to-time converter (VTC) enables linear zero-crossing interpolation in the time-domain with an interpolation factor of eight, resulting in reduced power consumption and area. A sequential slope-matching offset calibration scheme is proposed not only for VTC offset but also for interpolated zero-crossing accuracy. The prototype 6-bit 10-Gs/s 4x TI flash ADC was implemented in a 65-nm CMOS process and occupied 0.22 mm2 including a 4-to-1 output MUX and 243-times output decimator. The ADC achieves SNDR of 28.9 dB at Nyquist input and a total power consumption of 63 mW under supplies of 0.85 V and 1.1 V for the ADC cores and clock generator + T/Hs, respectively.
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一个6位10-GS/s 63mw 4x TI时域内插快闪ADC在65nm CMOS
提出了一种适用于高速应用的6-b 4倍时间交错(TI)时域插值flash ADC。动态放大器结构的电压-时间转换器(VTC)在时域内实现线性过零插值,插值系数为8,从而降低了功耗和面积。提出了一种序列斜率匹配偏置校正方案,不仅适用于VTC偏置,而且适用于插值过零精度。原型6位10-Gs/s 4x TI闪存ADC采用65纳米CMOS工艺实现,占地0.22 mm2,包括4对1输出MUX和243倍输出decimator。该ADC在Nyquist输入时的SNDR为28.9 dB,在0.85 V和1.1 V电源下的总功耗为63 mW,时钟发生器+ T/Hs。
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Theoretical analyses and modeling for nanoelectronics A 66 dB SNDR pipelined split-ADC using class-AB residue amplifier with analog gain correction Suppression of VCO pulling effects using even-harmonic quiet transmitting circuits A 6-bit 10-GS/s 63-mW 4x TI time-domain interpolating flash ADC in 65-nm CMOS A 0.01 mm2 fully-differential 2-stage amplifier with reference-free CMFB using an architecture-switching-scheme for bandwidth variation
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