Pub Date : 2015-11-12DOI: 10.1109/ESSDERC.2015.7324700
G. Baccarani, E. Baravelli, E. Gnani, A. Gnudi, S. Reggiani
In this presentation we shortly discuss the evolution of Microelectronics into Nanoelectronics, according to the predictions of Moore's law, and some of the issues related with this evolution. Next, we address the requirements of device modeling related with an extreme device miniaturization, such as the band splitting into multiple subbands and quasi-ballistic transport. Physical models are summarized and a few simulation results of heterojunction TFETs are reported and discussed.
{"title":"Theoretical analyses and modeling for nanoelectronics","authors":"G. Baccarani, E. Baravelli, E. Gnani, A. Gnudi, S. Reggiani","doi":"10.1109/ESSDERC.2015.7324700","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324700","url":null,"abstract":"In this presentation we shortly discuss the evolution of Microelectronics into Nanoelectronics, according to the predictions of Moore's law, and some of the issues related with this evolution. Next, we address the requirements of device modeling related with an extreme device miniaturization, such as the band splitting into multiple subbands and quasi-ballistic transport. Physical models are summarized and a few simulation results of heterojunction TFETs are reported and discussed.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78187518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313897
Alexander Fritsch, Michael Kugel, Rolf Sautter, D. Wendel, J. Pille, O. Torreiter, S. Kalyanasundaram, Daniel Dobson
A 4GHz, low latency TCAM in 14nm SOI FinFET technology, using a matchline current sensing scheme with an energy consumption of 0.63 fJ/bit/search at 0.9V and a peak current reduction of 50% compared to voltage sensing implementations. A by entry adjustable search depth allows to reduce power consumption for variable size translation tables. The implemented sandwich floorplan enables an area efficient integration of high performance 0.286μm2 16T-TCAM and 0.143μm2 8T-SRAM cells.
14nm SOI FinFET技术的4GHz低延迟TCAM，采用匹配线电流传感方案，在0.9V时能耗为0.63 fJ/bit/搜索，与电压传感实现相比，峰值电流降低50%。按条目可调的搜索深度允许减少可变大小翻译表的功耗。所实现的三明治平面设计实现了高性能0.286μm2 16T-TCAM和0.143μm2 8T-SRAM单元的面积高效集成。
{"title":"A 4GHz, low latency TCAM in 14nm SOI FinFET technology using a high performance current sense amplifier for AC current surge reduction","authors":"Alexander Fritsch, Michael Kugel, Rolf Sautter, D. Wendel, J. Pille, O. Torreiter, S. Kalyanasundaram, Daniel Dobson","doi":"10.1109/ESSCIRC.2015.7313897","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313897","url":null,"abstract":"A 4GHz, low latency TCAM in 14nm SOI FinFET technology, using a matchline current sensing scheme with an energy consumption of 0.63 fJ/bit/search at 0.9V and a peak current reduction of 50% compared to voltage sensing implementations. A by entry adjustable search depth allows to reduce power consumption for variable size translation tables. The implemented sandwich floorplan enables an area efficient integration of high performance 0.286μm2 16T-TCAM and 0.143μm2 8T-SRAM cells.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75162574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313845
Yue Wu, Tianyu Jia, B. Xia, Xinlong Ma, Li Kang, Xiaodong Yang
VCO TX pulling could seriously degrade transmitter performance. Unlike previous works that focus on alleviating the problem on the victim side(i.e. VCO or LO generator), we explored methods on suppressing the pulling tone generation at the transmitter side both magnetically and electrically. Magnetic differential structures and harmonic notch are employed for TX inductor/transformer and active circuits to reduce the pulling. Measurement results showed > 25dB reduction of pulling tone at +7dBm output power with <;10.5% DEVM_pk for 8-DPSK bluetooth modulation.
{"title":"Suppression of VCO pulling effects using even-harmonic quiet transmitting circuits","authors":"Yue Wu, Tianyu Jia, B. Xia, Xinlong Ma, Li Kang, Xiaodong Yang","doi":"10.1109/ESSCIRC.2015.7313845","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313845","url":null,"abstract":"VCO TX pulling could seriously degrade transmitter performance. Unlike previous works that focus on alleviating the problem on the victim side(i.e. VCO or LO generator), we explored methods on suppressing the pulling tone generation at the transmitter side both magnetically and electrically. Magnetic differential structures and harmonic notch are employed for TX inductor/transformer and active circuits to reduce the pulling. Measurement results showed > 25dB reduction of pulling tone at +7dBm output power with <;10.5% DEVM_pk for 8-DPSK bluetooth modulation.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73221320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313892
Dong-Ryeol Oh, Jong-In Kim, M. Seo, Jin-Gwang Kim, S. Ryu
A 6-b 4x time-interleaved (TI) time-domain interpolating flash ADC is presented for high-speed applications. The dynamic-amplifier-structured voltage-to-time converter (VTC) enables linear zero-crossing interpolation in the time-domain with an interpolation factor of eight, resulting in reduced power consumption and area. A sequential slope-matching offset calibration scheme is proposed not only for VTC offset but also for interpolated zero-crossing accuracy. The prototype 6-bit 10-Gs/s 4x TI flash ADC was implemented in a 65-nm CMOS process and occupied 0.22 mm2 including a 4-to-1 output MUX and 243-times output decimator. The ADC achieves SNDR of 28.9 dB at Nyquist input and a total power consumption of 63 mW under supplies of 0.85 V and 1.1 V for the ADC cores and clock generator + T/Hs, respectively.
{"title":"A 6-bit 10-GS/s 63-mW 4x TI time-domain interpolating flash ADC in 65-nm CMOS","authors":"Dong-Ryeol Oh, Jong-In Kim, M. Seo, Jin-Gwang Kim, S. Ryu","doi":"10.1109/ESSCIRC.2015.7313892","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313892","url":null,"abstract":"A 6-b 4x time-interleaved (TI) time-domain interpolating flash ADC is presented for high-speed applications. The dynamic-amplifier-structured voltage-to-time converter (VTC) enables linear zero-crossing interpolation in the time-domain with an interpolation factor of eight, resulting in reduced power consumption and area. A sequential slope-matching offset calibration scheme is proposed not only for VTC offset but also for interpolated zero-crossing accuracy. The prototype 6-bit 10-Gs/s 4x TI flash ADC was implemented in a 65-nm CMOS process and occupied 0.22 mm2 including a 4-to-1 output MUX and 243-times output decimator. The ADC achieves SNDR of 28.9 dB at Nyquist input and a total power consumption of 63 mW under supplies of 0.85 V and 1.1 V for the ADC cores and clock generator + T/Hs, respectively.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73306992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313819
B. Nikolić
Design of custom integrated circuits has become prohibitively expensive for many application domains. As a result, these domains often choose to implement the desired functionality on programmable platforms, but those solutions are less energy efficient. This paper proposes several approaches for making the design process more efficient and enabling custom energy-efficient integrated circuits. Function generators, as opposed to function instances, should be designed, which combined with higher-level design abstraction improve design efficiency and foster reuse. The use of generators also enables modular designs, aiding design verification. Rapid design flow maps generated modules into silicon and enables design-space exploration for optimal efficiency. Open-source repository of function generators and their mappings into systems allow designers to selectively add value to the design. These principles are demonstrated on a design of a processor, based on an open-source instruction set architecture, with integrated switched-capacitor DC-DC converters implemented in 28nm FDSOI. The chip is designed with a relatively small team and features high conversion efficiency (80-86%) and high energy efficiency (26.2 DP GFLOPS/W).
{"title":"Simpler, more efficient design","authors":"B. Nikolić","doi":"10.1109/ESSCIRC.2015.7313819","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313819","url":null,"abstract":"Design of custom integrated circuits has become prohibitively expensive for many application domains. As a result, these domains often choose to implement the desired functionality on programmable platforms, but those solutions are less energy efficient. This paper proposes several approaches for making the design process more efficient and enabling custom energy-efficient integrated circuits. Function generators, as opposed to function instances, should be designed, which combined with higher-level design abstraction improve design efficiency and foster reuse. The use of generators also enables modular designs, aiding design verification. Rapid design flow maps generated modules into silicon and enables design-space exploration for optimal efficiency. Open-source repository of function generators and their mappings into systems allow designers to selectively add value to the design. These principles are demonstrated on a design of a processor, based on an open-source instruction set architecture, with integrated switched-capacitor DC-DC converters implemented in 28nm FDSOI. The chip is designed with a relatively small team and features high conversion efficiency (80-86%) and high energy efficiency (26.2 DP GFLOPS/W).","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83406328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313872
D. Bol, E. Boufouss, D. Flandre, J. Vos
We propose an energy-harvesting management unit to interface a PV harvester with a storage supercapacitor while generating a 1V regulated supply VREG. Direct connection between stacked PV cells and VREG allows virtual 100% conversion efficiency between the harvester and the supplied circuits, while the use of a single bidirectional switched-capacitor DC/DC converter between VREG and the supercap allows 0.48mm2 area in a 65nm IoT vision SoC with a single external filtering capacitor. To cope with the 0-3V charge-dependent supercap voltage range and the wide 5μW-10mW harvester/load power range, the converter features adaptive selection between multiple voltage gains and power modes.
{"title":"A 0.48mm2 5μW-10mW indoor/outdoor PV energy-harvesting management unit in a 65nm SoC based on a single bidirectional multi-gain/multi-mode switched-cap converter with supercap storage","authors":"D. Bol, E. Boufouss, D. Flandre, J. Vos","doi":"10.1109/ESSCIRC.2015.7313872","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313872","url":null,"abstract":"We propose an energy-harvesting management unit to interface a PV harvester with a storage supercapacitor while generating a 1V regulated supply VREG. Direct connection between stacked PV cells and VREG allows virtual 100% conversion efficiency between the harvester and the supplied circuits, while the use of a single bidirectional switched-capacitor DC/DC converter between VREG and the supercap allows 0.48mm2 area in a 65nm IoT vision SoC with a single external filtering capacitor. To cope with the 0-3V charge-dependent supercap voltage range and the wide 5μW-10mW harvester/load power range, the converter features adaptive selection between multiple voltage gains and power modes.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80787991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313876
Taekwang Jang, Seokhyeon Jeong, M. Choi, Wanyeong Jung, Gyouho Kim, Yen-Po Chen, Yejoong Kim, Wootaek Lim, D. Sylvester, D. Blaauw
Recently, miniaturized sensor nodes have been widely studied for various applications. The advances in these studies have greatly reduced energy consumption, leading to a mm3-scale system and optimized circuit performance well suited for sensor node applications. This paper focuses on the ultra-low power circuit techniques on the major building blocks and demonstrates integration strategy of an image sensing platform.
{"title":"FOCUS: Key building blocks and integration strategy of a miniaturized wireless sensor node","authors":"Taekwang Jang, Seokhyeon Jeong, M. Choi, Wanyeong Jung, Gyouho Kim, Yen-Po Chen, Yejoong Kim, Wootaek Lim, D. Sylvester, D. Blaauw","doi":"10.1109/ESSCIRC.2015.7313876","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313876","url":null,"abstract":"Recently, miniaturized sensor nodes have been widely studied for various applications. The advances in these studies have greatly reduced energy consumption, leading to a mm3-scale system and optimized circuit performance well suited for sensor node applications. This paper focuses on the ultra-low power circuit techniques on the major building blocks and demonstrates integration strategy of an image sensing platform.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81067054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313837
Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
In this paper, an over Gb/s stochastic nonbinary LDPC (NB-LDPC) decoder chip is first-reported. The operation of proposed decoder is transformed to logarithm domain, so that the decoding complexity is mitigated by the simpler summations and fewer bit-width. In addition, the storage requirements are dramatically reduced by truncated TFM architecture. After, benefited from architecture optimizations and symbol-serial property, the routing capability of proposed decoder is extraordinarily enhanced. According to the measurement results, this decoder can deliver 1.31Gb/s throughput under 368MHz clock frequency with the corresponding energy-efficiency of 0.45nJ/bit. Compared to other NB-LDPC decoders, our stochastic NB-LDPC decoder with 96.6% chip utilization improves 2x area-efficiency and 7x energy-efficiency.
{"title":"A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications","authors":"Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee","doi":"10.1109/ESSCIRC.2015.7313837","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313837","url":null,"abstract":"In this paper, an over Gb/s stochastic nonbinary LDPC (NB-LDPC) decoder chip is first-reported. The operation of proposed decoder is transformed to logarithm domain, so that the decoding complexity is mitigated by the simpler summations and fewer bit-width. In addition, the storage requirements are dramatically reduced by truncated TFM architecture. After, benefited from architecture optimizations and symbol-serial property, the routing capability of proposed decoder is extraordinarily enhanced. According to the measurement results, this decoder can deliver 1.31Gb/s throughput under 368MHz clock frequency with the corresponding energy-efficiency of 0.45nJ/bit. Compared to other NB-LDPC decoders, our stochastic NB-LDPC decoder with 96.6% chip utilization improves 2x area-efficiency and 7x energy-efficiency.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90737387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313902
Hesong Xu, M. Perenzoni, N. Massari, A. Gola, A. Ferri, D. Stoppa
This paper presents a read-out chip for Silicon Photomultipliers (SiPMs) targeting Positron Emission Tomography (PET) application. The ASIC contains 16 channels, each consisting of a current buffer, a charge sensitive amplifier, a digital validation block, a 10-bit ADC and a 12-bit TDC with 45-ps resolution. The ASIC was realized in a 0.15μm CMOS technology, and has a size of 2.8×2.2 mm2. The high input charge range (11.5nC) was designed for a wide range of SiPM cell gain and size, from 15μm to 50μm, and for a maximum input current of 20mA per channel. The proposed double-trigger event validation allows setting the triggering threshold at a very low level, for optimal photon arrival time statistics in the scintillation light readout. Also the recovery time in each channel is reduced down to 30ns. Characterization results with a 511keV gamma source show an energy resolution of 11.2% with 3×3mm2 SiPMs coupled to 3×3×5mm3 LYSO scintillator and coincidence timing resolution of 663ps.
{"title":"A 30-ns recovery time, 11.5-nC input charge range, 16-channel read-out ASIC for PET application","authors":"Hesong Xu, M. Perenzoni, N. Massari, A. Gola, A. Ferri, D. Stoppa","doi":"10.1109/ESSCIRC.2015.7313902","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313902","url":null,"abstract":"This paper presents a read-out chip for Silicon Photomultipliers (SiPMs) targeting Positron Emission Tomography (PET) application. The ASIC contains 16 channels, each consisting of a current buffer, a charge sensitive amplifier, a digital validation block, a 10-bit ADC and a 12-bit TDC with 45-ps resolution. The ASIC was realized in a 0.15μm CMOS technology, and has a size of 2.8×2.2 mm2. The high input charge range (11.5nC) was designed for a wide range of SiPM cell gain and size, from 15μm to 50μm, and for a maximum input current of 20mA per channel. The proposed double-trigger event validation allows setting the triggering threshold at a very low level, for optimal photon arrival time statistics in the scintillation light readout. Also the recovery time in each channel is reduced down to 30ns. Characterization results with a 511keV gamma source show an energy resolution of 11.2% with 3×3mm2 SiPMs coupled to 3×3×5mm3 LYSO scintillator and coincidence timing resolution of 663ps.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90724085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313859
J. Wittmann, A. Barner, Thoralf Rosahl, B. Wicht
This paper presents an integrated synchronous buck converter for input voltages >12V with 10MHz switching frequency. The converter comprises a predictive dead time control with frequency compensated sampling of the switching node which does not require body diode forward conduction. A high dead time resolution of 125ps is achieved by a differential delay chain with 8-bit resolution. This way, the efficiency of fast switching DCDC converters can be optimized by eliminating the body diode forward conduction losses, minimizing reverse recovery losses and by achieving zero voltage switching at turn off. The converter was implemented in a 180nm high-voltage BiCMOS technology. The power losses were measured to be reduced by 30% by the proposed dead time control, which results in a 6% efficiency increase at VOUT = 5V and 0.2 A load. The peak efficiency is 81%.
{"title":"A 12V 10MHz buck converter with dead time control based on a 125 ps differential delay chain","authors":"J. Wittmann, A. Barner, Thoralf Rosahl, B. Wicht","doi":"10.1109/ESSCIRC.2015.7313859","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313859","url":null,"abstract":"This paper presents an integrated synchronous buck converter for input voltages >12V with 10MHz switching frequency. The converter comprises a predictive dead time control with frequency compensated sampling of the switching node which does not require body diode forward conduction. A high dead time resolution of 125ps is achieved by a differential delay chain with 8-bit resolution. This way, the efficiency of fast switching DCDC converters can be optimized by eliminating the body diode forward conduction losses, minimizing reverse recovery losses and by achieving zero voltage switching at turn off. The converter was implemented in a 180nm high-voltage BiCMOS technology. The power losses were measured to be reduced by 30% by the proposed dead time control, which results in a 6% efficiency increase at VOUT = 5V and 0.2 A load. The peak efficiency is 81%.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91196482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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