G. Servalli, D. Brazzelli, E. Camerlenghi, G. Capetti, S. Costantini, C. Cupeta, D. DeSimone, A. Ghetti, T. Ghilardi, P. Gulli, M. Mariani, A. Pavan, R. Somaschini
{"title":"A 65nm NOR flash technology with 0.042/spl mu/m/sup 2/ cell size for high performance multilevel application","authors":"G. Servalli, D. Brazzelli, E. Camerlenghi, G. Capetti, S. Costantini, C. Cupeta, D. DeSimone, A. Ghetti, T. Ghilardi, P. Gulli, M. Mariani, A. Pavan, R. Somaschini","doi":"10.1109/IEDM.2005.1609490","DOIUrl":null,"url":null,"abstract":"A 65nm NOR flash technology, featuring a true 10lambda2 , 0.042mum2 cell, is presented for the first time for 1bit/cell and 2bit/cell products. Advanced 193nm lithography, floating gate self aligned STI, cobalt salicide and three levels of copper metallization allow the integration with a high density and high performance 1.8V CMOS","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"6 1","pages":"849-852"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"24","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2005.1609490","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 24
Abstract
A 65nm NOR flash technology, featuring a true 10lambda2 , 0.042mum2 cell, is presented for the first time for 1bit/cell and 2bit/cell products. Advanced 193nm lithography, floating gate self aligned STI, cobalt salicide and three levels of copper metallization allow the integration with a high density and high performance 1.8V CMOS
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