G. Buh, T. Park, G. Yon, G. Kim, B. Koo, C. Ryoo, S. Hong, J.R. Yoo, J. Lee, Y. Shin, U. Chung, J. Moon, B. Ryu
{"title":"Interface states as an active component for 20 nm gate-length planar MOSFET with electrostatic channel extension (ESCE)","authors":"G. Buh, T. Park, G. Yon, G. Kim, B. Koo, C. Ryoo, S. Hong, J.R. Yoo, J. Lee, Y. Shin, U. Chung, J. Moon, B. Ryu","doi":"10.1109/IEDM.2005.1609485","DOIUrl":null,"url":null,"abstract":"Electrostatic channel extension (ESCE) MOSFET, a transistor with static inversion layer formed by interface fixed charge is fabricated in planar bulk structure down to 20 nm gate-length. The 24 nm gate-length ESCE transistor with current 80 nm gate-length SRAM technology shows the excellent drive currents of 1.0 mA/mum with IOFF of 93 nA/mum at VDS = 1 V. Moreover, the ESCE transistor with the gate oxide thickness of 10 Aring shows effectively suppressed gate-oxide leakage, very low GIDL, high breakdown voltage (> 6 V), immunity from CD variance, and robust reliability. The ESCE scheme is very promising to overcome the scale-down limit of planar transistor beyond 20 nm with ultra-low cost","PeriodicalId":13071,"journal":{"name":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","volume":"28 1","pages":"832-835"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2005.1609485","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Electrostatic channel extension (ESCE) MOSFET, a transistor with static inversion layer formed by interface fixed charge is fabricated in planar bulk structure down to 20 nm gate-length. The 24 nm gate-length ESCE transistor with current 80 nm gate-length SRAM technology shows the excellent drive currents of 1.0 mA/mum with IOFF of 93 nA/mum at VDS = 1 V. Moreover, the ESCE transistor with the gate oxide thickness of 10 Aring shows effectively suppressed gate-oxide leakage, very low GIDL, high breakdown voltage (> 6 V), immunity from CD variance, and robust reliability. The ESCE scheme is very promising to overcome the scale-down limit of planar transistor beyond 20 nm with ultra-low cost
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