{"title":"A low kickback noise and low power dynamic comparator","authors":"Bibhudutta Satapathy, Amandeep Kaur","doi":"10.1109/MWSCAS47672.2021.9531668","DOIUrl":null,"url":null,"abstract":"A low kickback noise and low power dynamic comparator is proposed in this paper. The designed comparator uses the current recycling approach to save power and proposes two kickback noise reduction techniques using only two additional switches. The technique I reduces the kickback noise from 20 mV to 7 mV and technique II reduces from 20 mV to 3 mV while consuming 11 µW and 21 µW, respectively of power. The proposed comparator is designed and simulated in UMC 180 nm CMOS process and is verified across the process corners. It operates at 100 MHz frequency and has an input range of 1 V. Monte Carlo simulations are also performed for the proposed techniques to test the design robustness.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"7 1","pages":"146-149"},"PeriodicalIF":0.0000,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS47672.2021.9531668","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A low kickback noise and low power dynamic comparator is proposed in this paper. The designed comparator uses the current recycling approach to save power and proposes two kickback noise reduction techniques using only two additional switches. The technique I reduces the kickback noise from 20 mV to 7 mV and technique II reduces from 20 mV to 3 mV while consuming 11 µW and 21 µW, respectively of power. The proposed comparator is designed and simulated in UMC 180 nm CMOS process and is verified across the process corners. It operates at 100 MHz frequency and has an input range of 1 V. Monte Carlo simulations are also performed for the proposed techniques to test the design robustness.
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