Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531770
J. Wagner, Takashi Miki, M. Ortmanns
In this paper an analysis of the influence of finite GBW in positive-feedback single-OpAmp resonator based CT BPSDMs is presented. The resonators of BPSDMs are often realized by LC tanks, requiring large area for the inductor. Positive-feedback single-OpAmp resonators are trying to solve this drawback, as no inductor is required. However, a large GBW of the OpAmp is necessary to achieve a sufficiently large quality factor. In this work, a system-level model accounting for finite GBW and DC gain for this type of resonator is presented. It allows the full compensation of finite GBW by a newly introduced system-level parameter. By implementing this model in a design environment for BPSDMs, a straightforward and automated design process in the CT domain can be carried out including loopfilter synthesis and STF engineering.
{"title":"Compensation of Finite GBW in CT Bandpass SDMs based on Single-OpAmp Resonators with Positive-Feedback","authors":"J. Wagner, Takashi Miki, M. Ortmanns","doi":"10.1109/MWSCAS47672.2021.9531770","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531770","url":null,"abstract":"In this paper an analysis of the influence of finite GBW in positive-feedback single-OpAmp resonator based CT BPSDMs is presented. The resonators of BPSDMs are often realized by LC tanks, requiring large area for the inductor. Positive-feedback single-OpAmp resonators are trying to solve this drawback, as no inductor is required. However, a large GBW of the OpAmp is necessary to achieve a sufficiently large quality factor. In this work, a system-level model accounting for finite GBW and DC gain for this type of resonator is presented. It allows the full compensation of finite GBW by a newly introduced system-level parameter. By implementing this model in a design environment for BPSDMs, a straightforward and automated design process in the CT domain can be carried out including loopfilter synthesis and STF engineering.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"29 1","pages":"284-287"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73726926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531927
Jatin Sharma, P. Verma, D. Mallick, Ankesh Jain
This work investigates the idea of using electrical energy injection for nonlinear mechanical energy harvesters (MEH). The system level analysis and device simulations suggest an improved performance can be obtained by selectively injecting an external signal. It further explores the possibility of using a hybrid MEH device combining piezoelectric and electromagnetic transducers to implement the proposed electrical energy injection method. The hybrid SECE technique is used to design the power management interface circuitry which also performs the energy injection. The designed circuits are simulated using CMOS 180 nm process and in region of multi-stability, it shows peak improvement in device output voltage around 6x time and in extracted power around 40-80x compared to conventional hybrid SECE energy harvesting technique.
{"title":"Electrical Energy Injection using Hybrid SECE for High Performance Nonlinear Mechanical Energy Harvesting","authors":"Jatin Sharma, P. Verma, D. Mallick, Ankesh Jain","doi":"10.1109/MWSCAS47672.2021.9531927","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531927","url":null,"abstract":"This work investigates the idea of using electrical energy injection for nonlinear mechanical energy harvesters (MEH). The system level analysis and device simulations suggest an improved performance can be obtained by selectively injecting an external signal. It further explores the possibility of using a hybrid MEH device combining piezoelectric and electromagnetic transducers to implement the proposed electrical energy injection method. The hybrid SECE technique is used to design the power management interface circuitry which also performs the energy injection. The designed circuits are simulated using CMOS 180 nm process and in region of multi-stability, it shows peak improvement in device output voltage around 6x time and in extracted power around 40-80x compared to conventional hybrid SECE energy harvesting technique.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"57 1","pages":"80-83"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74124273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531705
Brad Jolly
The internet of things (IoT) continues to grow quickly, with corresponding pressures to get products to market rapidly. Battery life is a key challenge, along with connectivity, coexistence, compliance, and cybersecurity. While traditional battery charge consumption measurement technologies use high speed measurements for optimal accuracy, slower measurements may actually be preferable under certain conditions. IoT devices operate in highly variable and dynamic environments that include changes to the physical environment, the electromagnetic environment, and the volumes of data measured, processed, stored, transmitted, and received. In many IoT applications there are serious consequences for the end user or device vendor if a device battery fails prematurely. This paper describes a hybrid strategy using event-based power analysis for measuring and analyzing an IoT device in highly dynamic environments. Engineers can use this hybrid approach to quickly gain the necessary insights to properly configure hardware, firmware, and software to optimize battery runtime and avoid customer frustration and the associated consequences.
{"title":"IoT Device Battery Life: Go Slow for Fast Insights Into Challenging Conditions","authors":"Brad Jolly","doi":"10.1109/MWSCAS47672.2021.9531705","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531705","url":null,"abstract":"The internet of things (IoT) continues to grow quickly, with corresponding pressures to get products to market rapidly. Battery life is a key challenge, along with connectivity, coexistence, compliance, and cybersecurity. While traditional battery charge consumption measurement technologies use high speed measurements for optimal accuracy, slower measurements may actually be preferable under certain conditions. IoT devices operate in highly variable and dynamic environments that include changes to the physical environment, the electromagnetic environment, and the volumes of data measured, processed, stored, transmitted, and received. In many IoT applications there are serious consequences for the end user or device vendor if a device battery fails prematurely. This paper describes a hybrid strategy using event-based power analysis for measuring and analyzing an IoT device in highly dynamic environments. Engineers can use this hybrid approach to quickly gain the necessary insights to properly configure hardware, firmware, and software to optimize battery runtime and avoid customer frustration and the associated consequences.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"16 1","pages":"680-683"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73046738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531738
V. S. Adhin, Arunjo Maliekkal, K. Mukilan, K. Sanjay, R. Chitra, A. P. James
Side-channel attacks are easy to execute and very hard to detect because of their passive nature. If the side channels can be used to decode the device operation, the same can be used to identify the physical property difference of the devices. We investigated the possibility of differentiating the devices based on acoustic side-channel attacks. The Mel Frequency Cepstral Coefficients (MFCC) acoustic features are extracted from the audio samples recorded from different computing devices including embedded modules, laptops, and PCs. A comparative analysis of classification accuracy for the various machine learning algorithms in terms of Precision and Recall is also presented. Our results show that CNN and LSTM give the desired results with better accuracy among the different classification models considered.
{"title":"Acoustic Side Channel Attack for Device Identification using Deep Learning Models","authors":"V. S. Adhin, Arunjo Maliekkal, K. Mukilan, K. Sanjay, R. Chitra, A. P. James","doi":"10.1109/MWSCAS47672.2021.9531738","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531738","url":null,"abstract":"Side-channel attacks are easy to execute and very hard to detect because of their passive nature. If the side channels can be used to decode the device operation, the same can be used to identify the physical property difference of the devices. We investigated the possibility of differentiating the devices based on acoustic side-channel attacks. The Mel Frequency Cepstral Coefficients (MFCC) acoustic features are extracted from the audio samples recorded from different computing devices including embedded modules, laptops, and PCs. A comparative analysis of classification accuracy for the various machine learning algorithms in terms of Precision and Recall is also presented. Our results show that CNN and LSTM give the desired results with better accuracy among the different classification models considered.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"6 1","pages":"857-860"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73581896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Approximate computing (AC) provides an efficient solution for reducing power, area, and complexity of digital systems. When backed with distributed arithmetic (DA), AC leverages the ability to implement ultra-efficient inner-product units in terms of area, power, and delay. Such units can be used in any inherently resilient application. This paper presents a novel scheme of approximate inner-product based on parallel DA for low-power fault-tolerant applications backed with a novel in-situ sliding window algorithm. Our model eliminates the need for an explicit error correction scheme, which further reduces the overhead while improving the accuracy. The experimental results show that our model achieves a state-of-the-art performance in terms of power delay product (PDP), area power product (APP) with a reduction of 39.26% and 48.83%, respectively.
{"title":"An In-Situ Sliding Window Approximate Inner-Product Scheme Based on Parallel Distributed Arithmetic for Ultra-Low Power Fault-Tolerant Applications","authors":"Dominick Rizk, Rodrigue Rizk, Frederic Rizk, Ashok Kumar","doi":"10.1109/MWSCAS47672.2021.9531886","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531886","url":null,"abstract":"Approximate computing (AC) provides an efficient solution for reducing power, area, and complexity of digital systems. When backed with distributed arithmetic (DA), AC leverages the ability to implement ultra-efficient inner-product units in terms of area, power, and delay. Such units can be used in any inherently resilient application. This paper presents a novel scheme of approximate inner-product based on parallel DA for low-power fault-tolerant applications backed with a novel in-situ sliding window algorithm. Our model eliminates the need for an explicit error correction scheme, which further reduces the overhead while improving the accuracy. The experimental results show that our model achieves a state-of-the-art performance in terms of power delay product (PDP), area power product (APP) with a reduction of 39.26% and 48.83%, respectively.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"11 1","pages":"503-506"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74325009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531829
Yuekang Guo, J. Jin, Jianjun J. Zhou
This paper presents a low power technique to solve the gain variation problem of the dynamic amplifiers in pipelined SAR ADCs. To detect and correct the gain variation of the dynamic amplifier across different process, voltage, and temperature (PVT) corners, an amplification path parallel to the dynamic amplifier is added as a reference for comparison of voltage gain. To achieve high PVT-robustness and power-efficiency, a two-stage passive amplification path is proposed as the reference path. Designed in 40 nm CMOS process, across different PVT corners the gain variation of the dynamic amplifier and the SNDR degradation of the ADC are less than ±1.1% and 1 dB, respectively. The extra circuits for the stabilization technique only consume 18% of the power consumption of the dynamic amplifier.
{"title":"A Low Power PVT Stabilization Technique for Dynamic Amplifier in Pipelined SAR ADC","authors":"Yuekang Guo, J. Jin, Jianjun J. Zhou","doi":"10.1109/MWSCAS47672.2021.9531829","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531829","url":null,"abstract":"This paper presents a low power technique to solve the gain variation problem of the dynamic amplifiers in pipelined SAR ADCs. To detect and correct the gain variation of the dynamic amplifier across different process, voltage, and temperature (PVT) corners, an amplification path parallel to the dynamic amplifier is added as a reference for comparison of voltage gain. To achieve high PVT-robustness and power-efficiency, a two-stage passive amplification path is proposed as the reference path. Designed in 40 nm CMOS process, across different PVT corners the gain variation of the dynamic amplifier and the SNDR degradation of the ADC are less than ±1.1% and 1 dB, respectively. The extra circuits for the stabilization technique only consume 18% of the power consumption of the dynamic amplifier.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"32 1","pages":"18-21"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77280790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531864
E. I. Barros, O. J. Cinco-Izquierdo, M. T. Sanz
This paper presents a first-order low-pass filter with tunable cut-off frequency and programmable gain. The proposed circuit is based on a super-source follower transconductor, with a current steering second stage. The circuit was designed in a standard 0.18µm CMOS process with a power consumption of 2.99µW for a power supply of 1.8V . The filter shows a tunable frequency from 560 Hz to 22 kHz, with programmable gain from 6 to 20 dB.
提出了一种截止频率可调、增益可编程的一阶低通滤波器。所提出的电路是基于一个超源跟随式变换器，具有电流转向第二阶段。该电路采用标准的0.18 μ m CMOS工艺，功耗为2.99 μ W，电源为1.8V。该滤波器显示从560hz到22khz的可调频率，具有6到20db的可编程增益。
{"title":"A Low-Frequency LPF with Programmable Gain and Tunable Cut-off Frequency","authors":"E. I. Barros, O. J. Cinco-Izquierdo, M. T. Sanz","doi":"10.1109/MWSCAS47672.2021.9531864","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531864","url":null,"abstract":"This paper presents a first-order low-pass filter with tunable cut-off frequency and programmable gain. The proposed circuit is based on a super-source follower transconductor, with a current steering second stage. The circuit was designed in a standard 0.18µm CMOS process with a power consumption of 2.99µW for a power supply of 1.8V . The filter shows a tunable frequency from 560 Hz to 22 kHz, with programmable gain from 6 to 20 dB.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"31 1","pages":"424-427"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80007827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Charge pump (CP) based PLL is one of the most popular techniques because of its wide capture range and zero static phase offset. An op-amp is used to achieve dynamic current matching in the conventional double op-amp CP. This paper proposes a CP, which adopts simple level shift source follower to match the output voltages of two current mirrors when the output voltage of CP changes. Because one of the high-speed op-amps is deleted, the power consumption and area are cut down without sacrificing the current matching performance. The proposed CP achieves less than 0.025% DC current mismatch with 400 μA charge pump current under 1.2V supply when the output voltage changes from 0.3V to 0.9V in a standard 55 nm CMOS process.
{"title":"A 0.025% DC Current Mismatch Charge Pump for PLL Applications","authors":"Shengyu Liang, Youze Xin, Chenglong Liang, Bing Zhang, Yanlong Zhang, Xiaoli Wang, Li Geng","doi":"10.1109/MWSCAS47672.2021.9531880","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531880","url":null,"abstract":"Charge pump (CP) based PLL is one of the most popular techniques because of its wide capture range and zero static phase offset. An op-amp is used to achieve dynamic current matching in the conventional double op-amp CP. This paper proposes a CP, which adopts simple level shift source follower to match the output voltages of two current mirrors when the output voltage of CP changes. Because one of the high-speed op-amps is deleted, the power consumption and area are cut down without sacrificing the current matching performance. The proposed CP achieves less than 0.025% DC current mismatch with 400 μA charge pump current under 1.2V supply when the output voltage changes from 0.3V to 0.9V in a standard 55 nm CMOS process.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"474 1","pages":"700-703"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80251344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531866
Daniel Junehee Lee, F. Yuan, Yushi Zhou
An 8-bit time-mode pseudo-differential successive approximation register time-to-digital converter (SAR TDC) is presented. The TDC achieves a high resolution and a better power/area efficiency using a pair of 16-stage pre-skewed delay line for 4-bit coarse digital-to-time conversion and a pair of digital time interpolators for 4-bit fine digital-to-time conversion. The architecture, operation, and design details of the TDC are provided. The pseudo-differential signaling of the TDC is examined and timing errors caused by device noise are studied. The TDC is designed in a TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM3.3 device models. Simulation results show the TDC achieves 6.6 ps resolution, 7.1 ENOB, and 0.37 pJ/conversion FOM at 10 MS/s.
{"title":"Successive Approximation Register TDC in Time-Mode Signal Processing","authors":"Daniel Junehee Lee, F. Yuan, Yushi Zhou","doi":"10.1109/MWSCAS47672.2021.9531866","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531866","url":null,"abstract":"An 8-bit time-mode pseudo-differential successive approximation register time-to-digital converter (SAR TDC) is presented. The TDC achieves a high resolution and a better power/area efficiency using a pair of 16-stage pre-skewed delay line for 4-bit coarse digital-to-time conversion and a pair of digital time interpolators for 4-bit fine digital-to-time conversion. The architecture, operation, and design details of the TDC are provided. The pseudo-differential signaling of the TDC is examined and timing errors caused by device noise are studied. The TDC is designed in a TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM3.3 device models. Simulation results show the TDC achieves 6.6 ps resolution, 7.1 ENOB, and 0.37 pJ/conversion FOM at 10 MS/s.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"37 1","pages":"945-948"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79162500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531742
Qiang Pan, Yuekang Guo, J. Jin, Jianjun J. Zhou
This paper presents a power-efficient linearization technique based on bulk-modulation for the voltage-to-frequency conversion characteristic of the ring voltage-controlled oscillator (VCO), which can be easily adopted in VCO-based analog-to-digital converters (ADCs) to achieve high resolution. A bulk-control voltage generator is utilized to modulate the threshold voltages of the VCO input transistors. Combined with the conventional gate-control scheme, the nonlinearity of the VCO can be reduced effectively. A second-order sigma-delta ADC with proposed linearized VCO is implemented in 0.18μm CMOS technology to verify the effectiveness. Simulation results show the nonlinearity of the VCO drops from 10% to 2% and the total distortion can be reduced by 19dB through bulk-modulation compared with conventional VCO.
{"title":"A Linearization Technique for Ring VCO Exploiting Bulk-Modulation","authors":"Qiang Pan, Yuekang Guo, J. Jin, Jianjun J. Zhou","doi":"10.1109/MWSCAS47672.2021.9531742","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531742","url":null,"abstract":"This paper presents a power-efficient linearization technique based on bulk-modulation for the voltage-to-frequency conversion characteristic of the ring voltage-controlled oscillator (VCO), which can be easily adopted in VCO-based analog-to-digital converters (ADCs) to achieve high resolution. A bulk-control voltage generator is utilized to modulate the threshold voltages of the VCO input transistors. Combined with the conventional gate-control scheme, the nonlinearity of the VCO can be reduced effectively. A second-order sigma-delta ADC with proposed linearized VCO is implemented in 0.18μm CMOS technology to verify the effectiveness. Simulation results show the nonlinearity of the VCO drops from 10% to 2% and the total distortion can be reduced by 19dB through bulk-modulation compared with conventional VCO.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"81 1","pages":"737-740"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76913480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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