{"title":"A novel high speed and high current FET driver with floating ground and integrated charge pump","authors":"J. Xu, Lin Sheng, Xianhui Dong","doi":"10.1109/ECCE.2012.6342393","DOIUrl":null,"url":null,"abstract":"This paper presents a new high speed Power FET driver with 5A sourcing and sinking current capability and 20V rail-to-rail output range. Due to the 7V gate oxide breakdown limitation of process, a floating ground inside the driver is created to drive the pull-up N-type LDMOS. With this floating ground, the pull-up N-type LDMOS can be driven separately from the pull-down N-type LDMOS and the driver is free of shoot-through current. In order to minimize the rise time during switching, a charge pump circuit is implemented to bring the gate voltage of pull-up N-type LDMOS above the supply rail. As a result, the driver's pull-up capability above power FET's miller plateau is improved largely and the rising time is reduced about 65% when VDD is 5V compared to the conventional driver. A 5A dual channel driver with the proposed novel scheme is designed, the die size is only 1mm×1mm and it has the leading edge performance over all the commercial products. The scheme, simulation and silicon test results are included in this paper.","PeriodicalId":6401,"journal":{"name":"2012 IEEE Energy Conversion Congress and Exposition (ECCE)","volume":"30 1","pages":"2604-2609"},"PeriodicalIF":0.0000,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE Energy Conversion Congress and Exposition (ECCE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECCE.2012.6342393","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
This paper presents a new high speed Power FET driver with 5A sourcing and sinking current capability and 20V rail-to-rail output range. Due to the 7V gate oxide breakdown limitation of process, a floating ground inside the driver is created to drive the pull-up N-type LDMOS. With this floating ground, the pull-up N-type LDMOS can be driven separately from the pull-down N-type LDMOS and the driver is free of shoot-through current. In order to minimize the rise time during switching, a charge pump circuit is implemented to bring the gate voltage of pull-up N-type LDMOS above the supply rail. As a result, the driver's pull-up capability above power FET's miller plateau is improved largely and the rising time is reduced about 65% when VDD is 5V compared to the conventional driver. A 5A dual channel driver with the proposed novel scheme is designed, the die size is only 1mm×1mm and it has the leading edge performance over all the commercial products. The scheme, simulation and silicon test results are included in this paper.