T. Hamamoto, S. Kawasaki, K. Furutani, K. Yasuda, Y. Konishi
{"title":"A skew and jitter suppressed DLL architecture for high frequency DDR SDRAMs","authors":"T. Hamamoto, S. Kawasaki, K. Furutani, K. Yasuda, Y. Konishi","doi":"10.1109/VLSIC.2000.852857","DOIUrl":null,"url":null,"abstract":"This paper demonstrates a skew and jitter suppressed delay locked loop (DLL) architecture used for over 400 Mbps operating DDR SDRAMs. Two novel replica adjusting techniques are introduced, which reduce timing skews between external clocks and data outputs. An improved delay line architecture is introduced, which realizes a high frequency and jitter suppressed DLL.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"75 1","pages":"76-81"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2000.852857","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
This paper demonstrates a skew and jitter suppressed delay locked loop (DLL) architecture used for over 400 Mbps operating DDR SDRAMs. Two novel replica adjusting techniques are introduced, which reduce timing skews between external clocks and data outputs. An improved delay line architecture is introduced, which realizes a high frequency and jitter suppressed DLL.
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