Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852851
Bo Shi, L. Sundstrom
The LINC transmitter provides linear amplification using nonlinear but power efficient amplifiers. The signal component separator (SCS) is a crucial function of LINC. This paper presents a 200 MHz IF SCS chip implemented in a 0.8 /spl mu/m BiCMOS process using a novel design based on translinear circuits. The experimental LINC transmitter, built with the chip and nonlinear amplifiers, had output spurious levels around -55 dBc for both a NADC signal and a PHS signal. This implies a high degree of linearity.
{"title":"A translinear-based chip for linear LINC transmitters","authors":"Bo Shi, L. Sundstrom","doi":"10.1109/VLSIC.2000.852851","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852851","url":null,"abstract":"The LINC transmitter provides linear amplification using nonlinear but power efficient amplifiers. The signal component separator (SCS) is a crucial function of LINC. This paper presents a 200 MHz IF SCS chip implemented in a 0.8 /spl mu/m BiCMOS process using a novel design based on translinear circuits. The experimental LINC transmitter, built with the chip and nonlinear amplifiers, had output spurious levels around -55 dBc for both a NADC signal and a PHS signal. This implies a high degree of linearity.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"16 1","pages":"58-61"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72762590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852864
Y. Yabe, N. Nakamura, Y. Aimoto, M. Motomura, Yasuhiro Matsui, Y. Adakura
As processor performance is reaching the level of executing a single instruction in 1 ns, long memory latencies have become a critical problem, because a single memory access could stall the execution of hundreds of instructions. A recently announced channeled-DRAM approaches this problem by integrating a small low-latency buffer, called "channels", in front of a DRAM core in order to reduce the effective memory latency. Since the channels can provide intrinsically faster access than that of a bare DRAM core when they hit, key considerations in this architecture become (1) how to achieve high channel hit rates and (2) how to reduce the channel-miss latencies. Since channeled-DRAMs rely on an external memory controller to handle all the channel management, design of the memory controller heavily dominates the first issue. In this paper, we propose two novel techniques for reducing the channel-miss latencies: direct background operation and delayed channel replacement. We examined these techniques in a future 256-Mb DRAM with a 200-MHz double-data-rate (DDR) synchronous interface. Both SPICE simulation results (that show channel-miss latency reduction) and system-level simulation results (that reveal system-level performance improvement) are presented.
{"title":"A next generation channeled-DRAM architecture with direct background-operation and delayed channel-replacement techniques","authors":"Y. Yabe, N. Nakamura, Y. Aimoto, M. Motomura, Yasuhiro Matsui, Y. Adakura","doi":"10.1109/VLSIC.2000.852864","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852864","url":null,"abstract":"As processor performance is reaching the level of executing a single instruction in 1 ns, long memory latencies have become a critical problem, because a single memory access could stall the execution of hundreds of instructions. A recently announced channeled-DRAM approaches this problem by integrating a small low-latency buffer, called \"channels\", in front of a DRAM core in order to reduce the effective memory latency. Since the channels can provide intrinsically faster access than that of a bare DRAM core when they hit, key considerations in this architecture become (1) how to achieve high channel hit rates and (2) how to reduce the channel-miss latencies. Since channeled-DRAMs rely on an external memory controller to handle all the channel management, design of the memory controller heavily dominates the first issue. In this paper, we propose two novel techniques for reducing the channel-miss latencies: direct background operation and delayed channel replacement. We examined these techniques in a future 256-Mb DRAM with a 200-MHz double-data-rate (DDR) synchronous interface. Both SPICE simulation results (that show channel-miss latency reduction) and system-level simulation results (that reveal system-level performance improvement) are presented.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"48 7 1","pages":"108-111"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75391713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852874
C. Paulus, R. Thewes
A universal linearization technique applicable to fast, nonlinear voltage-to-current converters (VCC) is presented. The method is based on a new circuit architecture combining a set of given basic VCCs with resistors which operate as linear current-to-voltage converters (CVC). The linearity of the resulting circuit is essentially improved compared to that of a single basic VCC with only small losses in conversion speed. Operational amplifiers are not required so that this approach is also applicable at low supply voltages. Experimental data are shown which demonstrate an improvement in linearity of approximately one decade.
{"title":"Linearization method for fast voltage-to-current converters","authors":"C. Paulus, R. Thewes","doi":"10.1109/VLSIC.2000.852874","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852874","url":null,"abstract":"A universal linearization technique applicable to fast, nonlinear voltage-to-current converters (VCC) is presented. The method is based on a new circuit architecture combining a set of given basic VCCs with resistors which operate as linear current-to-voltage converters (CVC). The linearity of the resulting circuit is essentially improved compared to that of a single basic VCC with only small losses in conversion speed. Operational amplifiers are not required so that this approach is also applicable at low supply voltages. Experimental data are shown which demonstrate an improvement in linearity of approximately one decade.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"1 1","pages":"144-145"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83005755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852849
V. Gutnik, A. Chandrakasan
A flash Time to Digital Converter (TDC) can be calibrated to a precision on the order of the arbiter aperature without precise input signals. A theoretical result useful for calibration of a noise-limited arbiter array is derived, and verified empirically. A test chip with 64 arbiters in a 0.35 /spl mu/m CMOS process shows temporal resolution better than 2 picoseconds.
{"title":"On-chip picosecond time measurement","authors":"V. Gutnik, A. Chandrakasan","doi":"10.1109/VLSIC.2000.852849","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852849","url":null,"abstract":"A flash Time to Digital Converter (TDC) can be calibrated to a precision on the order of the arbiter aperature without precise input signals. A theoretical result useful for calibration of a noise-limited arbiter array is derived, and verified empirically. A test chip with 64 arbiters in a 0.35 /spl mu/m CMOS process shows temporal resolution better than 2 picoseconds.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"24 1","pages":"52-53"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73568421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852858
A. Amerasekera
In this paper we review the present approaches to ESD for microprocessors and ASICs, and the different requirements and constraints for these chips. The evolution of these requirements in the next generations of ICs is discussed.
{"title":"Addressing ESD for microprocessors and ASICs in 21st century technologies","authors":"A. Amerasekera","doi":"10.1109/VLSIC.2000.852858","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852858","url":null,"abstract":"In this paper we review the present approaches to ESD for microprocessors and ASICs, and the different requirements and constraints for these chips. The evolution of these requirements in the next generations of ICs is discussed.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"89 1","pages":"84-87"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89053822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852855
A. Kawasumi, A. Suzuki, H. Hatada, Y. Takeyama, O. Hirabayashi, Y. Kameda, T. Hamano, N. Otsuka
In view of the remarkable progress in MPU performance, improvement in the data rate of L2 cache SRAMs is desirable to maximize system performance. As a solution, Double-Data-Rate (DDR) SRAMs, which can realize an I/O frequency of up to twice that of conventional Single-Data-Rate (SDR) SRAMs, have been reported. Increase in operation-current due to higher operation frequency causes severe power-line noise and heating. Therefore, reduction of operation-current is an important issue in designing high-speed SRAMs. In order to realize both high-frequency operation and power reduction, we propose new sense circuitry and a bit-line load scheme.
{"title":"A 1.8 V 18 Mb DDR CMOS SRAM with power reduction techniques","authors":"A. Kawasumi, A. Suzuki, H. Hatada, Y. Takeyama, O. Hirabayashi, Y. Kameda, T. Hamano, N. Otsuka","doi":"10.1109/VLSIC.2000.852855","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852855","url":null,"abstract":"In view of the remarkable progress in MPU performance, improvement in the data rate of L2 cache SRAMs is desirable to maximize system performance. As a solution, Double-Data-Rate (DDR) SRAMs, which can realize an I/O frequency of up to twice that of conventional Single-Data-Rate (SDR) SRAMs, have been reported. Increase in operation-current due to higher operation frequency causes severe power-line noise and heating. Therefore, reduction of operation-current is an important issue in designing high-speed SRAMs. In order to realize both high-frequency operation and power reduction, we propose new sense circuitry and a bit-line load scheme.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"66 1","pages":"72-73"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83915293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852886
Yibin Ye, J. Tschanz, S. Narendra, S. Borkar, M. Stan, V. De
Stack node preconditioning (SNP) and "mutex" techniques for charge-sharing noise reduction are incorporated into the critical path gates containing transistor stacks in 32-bit domino adders to simultaneously improve best achievable performance by 10% and reduce charge-sharing noise by 2/spl times/ in circuits containing transistor stacks.
{"title":"Comparative delay, noise and energy of high-performance domino adders with stack node preconditioning (SNP)","authors":"Yibin Ye, J. Tschanz, S. Narendra, S. Borkar, M. Stan, V. De","doi":"10.1109/VLSIC.2000.852886","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852886","url":null,"abstract":"Stack node preconditioning (SNP) and \"mutex\" techniques for charge-sharing noise reduction are incorporated into the critical path gates containing transistor stacks in 32-bit domino adders to simultaneously improve best achievable performance by 10% and reduce charge-sharing noise by 2/spl times/ in circuits containing transistor stacks.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"22 1","pages":"188-191"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85802075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852891
Y. Mitsuyama, Z. Andales, T. Onoye, I. Shirakawa
A cipher core has been implemented, which is dedicated to the 64-bit block, 128-bit key novel hardware-based cryptosystem called Chameleon. Chameleon adopts the approach that is distinctive for its two 32-cell, 8-context dynamically reconfigurable unit to generate subkeys for each of the 16 iterations of encryption process. The proposed cipher core has been integrated in the die area of 5.90 mm/sup 2/ by means of a 0.6 /spl mu/m CMOS 3 LM technology which attains a maximum throughput of 635 Mbps.
{"title":"VLSI implementation of dynamically reconfigurable hardware-based cryptosystem","authors":"Y. Mitsuyama, Z. Andales, T. Onoye, I. Shirakawa","doi":"10.1109/VLSIC.2000.852891","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852891","url":null,"abstract":"A cipher core has been implemented, which is dedicated to the 64-bit block, 128-bit key novel hardware-based cryptosystem called Chameleon. Chameleon adopts the approach that is distinctive for its two 32-cell, 8-context dynamically reconfigurable unit to generate subkeys for each of the 16 iterations of encryption process. The proposed cipher core has been integrated in the die area of 5.90 mm/sup 2/ by means of a 0.6 /spl mu/m CMOS 3 LM technology which attains a maximum throughput of 635 Mbps.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"47 1","pages":"204-205"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80517534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852842
D. Handoko, Shoji Kawahito, M. Kumahara, Akira Matsuzawa
This paper presents a CMOS image sensor which captures intermediate pictures at 480 frames/s and a fully accumulated picture at 30 frames/s. The CMOS image sensor is for integrating a low-power motion vector estimation (MVE) engine using the iterative block matching algorithm proposed by the authors.
{"title":"A CMOS image sensor for focal-plane low-power motion vector estimation","authors":"D. Handoko, Shoji Kawahito, M. Kumahara, Akira Matsuzawa","doi":"10.1109/VLSIC.2000.852842","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852842","url":null,"abstract":"This paper presents a CMOS image sensor which captures intermediate pictures at 480 frames/s and a fully accumulated picture at 30 frames/s. The CMOS image sensor is for integrating a low-power motion vector estimation (MVE) engine using the iterative block matching algorithm proposed by the authors.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"13 1","pages":"28-29"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78896562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-15DOI: 10.1109/VLSIC.2000.852875
Christopher W. Mangelsdorf
A variable gain amplifier architecture suitable for foundry CMOS is constructed using linearized transconductance blocks. The use of a four-transistor transconductance cell allows for wider gain range and larger signal swing under low supply conditions than the simple differential pair used in previous work. Experimental results with 0.6 /spl mu/m CMOS show -5 to 35 dB gain and 20 MHz bandwidth at 21 mW.
{"title":"A variable gain CMOS amplifier with exponential gain control","authors":"Christopher W. Mangelsdorf","doi":"10.1109/VLSIC.2000.852875","DOIUrl":"https://doi.org/10.1109/VLSIC.2000.852875","url":null,"abstract":"A variable gain amplifier architecture suitable for foundry CMOS is constructed using linearized transconductance blocks. The use of a four-transistor transconductance cell allows for wider gain range and larger signal swing under low supply conditions than the simple differential pair used in previous work. Experimental results with 0.6 /spl mu/m CMOS show -5 to 35 dB gain and 20 MHz bandwidth at 21 mW.","PeriodicalId":6361,"journal":{"name":"2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)","volume":"123 1","pages":"146-149"},"PeriodicalIF":0.0,"publicationDate":"2000-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76834749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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